Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The acid test of any conference is how long the information and lessons learned linger in your mind after the keynotes, panels, and demos wrap up. Like last year, the 2011 edition of ARM Techcon is passing the test of time. Below are some of the highlights that have stuck with me and/or have been prompted by follow-on news since the event.
This year's ARM Techcon highlighted advances on many fronts - semiconductor tech., business models and "apps", virtual prototypes, and record breaking Rubik's cube solving!
"The ARM v. Intel fight just got good": This headline borrowed from this short&sweet GigaOm piece on ARM's 64 bit architecture announcement hits the nail on the head whether you are talking about the mobile domain, or the less glamorous server-based processors. Specifically, everywhere you looked at Techcon there was something competitive, if not outright threatening, to "only the paranoid survive" Intel fans. Suffice to say both companies have their work cut out for them in this high-stakes competition that's unfolding at both the "macro" systems level, as well as the nanometer level (to wit: compare announcements of ARM-based 20 nm test chips vs. Intel's tantalizing hints of 14nm processes working in the lab). On this score it will be interesting to parse through the upcoming CES 2012 product & design win announcements to see how this competition is paying out.
Speaking of semi news from Techcon ...
Sub-20nm is the Rubicon: Long time followers of semiconductor technology are used to periodic "sky is falling" comments (remember the "electromigration crisis"?). However, in two different keynote speeches it was made clear that below 20nm it truly is a brave new world. First, I was struck by the blunt clarity of TSMC's CEO Dr. Shang-Yi Chiang's statement that "20nm is the last generation of planar transistor." Later that morning, Cadence's Chi-Ping Hsu's keynote titled "High Stakes at Low Process Nodes" drove home the consequences of this statement in a myriad of ways. Perhaps due to my EDA-origins, one 20nm discontinuity that stuck with me is that 20nm design adds more than 400 design rules to the layout process. Reinforcing Dr. Chiang's statement with a few simple examples of these seemingly contradictory rules, he dramatized how layout is now even more of a 3D chess puzzle than ever. As such, Chi-Ping's assertion that the "aggregate EDA tool development costs ... are estimated at $400-$500 million at 32/28nm and $800 million - $1.2B at 22/20nm" seem like underestimates, if anything.
New Avnet & ARM software store shows EDA360 in action: When long time component distributor Avnet partners with IP leader ARM to leap into the software services business, you know that the electronics industry's tectonic plates have shifted by a few yards. Specifically, the announcement of a new embedded software app store seems like it was torn out of the pages of the EDA360 vision document, where Avnet realized that there is money to be made by enabling their customers to "differentiate silicon with software" as so crisply stated by Harvey Feldberg in his keynote.
"Look Ma, no hardware" with Virtual Software Prototyping: As the many vendors writing apps for the aforementioned embedded software store can no doubt attest, the plethora of processing options and low cost of processors in general are drastically complicating the system development task. Fortunately, virtual prototyping - i.e. complete system models that enable software development and debugging before system hardware is available - took a quantum leap at Techcon with the introduction of the "Virtual System Platform" by my colleague and Cadence R&D Architect Jason Andrews. In his paper on "Creation and Usage of SystemC Virtual Platforms for Multi-Core System Debugging and Analysis", Jason showed a no-kidding case of how this new platform can simultaneously help everyone from system architects, pure software coders, and RTL developers, get the design and debug information they need in the format that they are most comfortable using. (In addition to the written paper in the conference proceedings, a video of Jason's presentation is publicly available on YouTube. Jason is an engineer's engineer, so while the video is 47 minutes it's no-hype, productive lunchtime viewing.)
Lego Rubik's cube robot: last but not least, I must again tip my hat to the world-record breaking "CubeStormer II". It's such a fun display of ARM's expertise that my product team has replicated the idea using our formal verification product as the "brain" of our own (mechanically slower) Lego robot - coming soon to a trade show near you ...
Finally, included below are some additional links to high-value ARM Techcon-related articles, blogs, and videos.Until next year, may your power consumption be low and your throughput be high!
Joe Hupcey III
Twitter: @jhupcey, http://twitter.com/jhupcey
More from Richard Goering's "Industry Insights" column: ARM TechCon Highlights Roundup - Blogs, Videos, and More
Highlights from Steve Leibson, the "EDA360 Insider"
"Charbax's" (a/k/a Nicolas Charbonnier of ARMdevices.net) catalog of ARM Techcon video blog entries
Smith: ARM TECHCON 2011 - The Week The World Changedhttp://www.garysmitheda.com/read.php?story=iNotes_106
Chips Away at Intel's Server Business!