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Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology (UVM) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that build on the UVM to serve the requirements of advanced node SoCs.
The Accellera Systems Initiative UVM is gaining great momentum in the industry. From the Cadence perspective, our customers starting new SystemVerilog projects are doing so with UVM, and those starting new e projects are doing so with our e-based equivalent. Those customers are enjoying the reuse that is built into the UVM and the Cadence differentiators that work with the UVM like verification IP and debug. But the wise verification lead faced with low-power, massive designs, multi-language IP, and more challenges that seem to be prevalent at 40nm and below is asking -- what's next?
The Advanced Verification Topics book describes what's next. The five chapters, expertly described by Richard Goering in his blog, introduce methodologies that will improve productivity, predictability, and quality building on the UVM methodology base. Verification engineers reading this book will gain an appreciation for the work that needs to be done to implement these methodologies and the potential gains they represent.
In stark contrast to Mr. Duell's quote, Cadence has only just begun. Watch us in 2012 as we introduce several other topics and expand the languages used in our examples. We have a bigger boast for verification -- everything that can be invented WILL be invented and quite likely it will be from the engineers at Cadence.
=Adam Sherer, MS EE, BS EE, BA CS
** Note: Dennis Crouch's research suggests the quote actually comes from a 1899 humor magazine that described a fictitious exchange between a genius and a young lad at the patent office.