Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
In addition to the annotated image gallery (click here or on the image), or the playlist of videos on some of the papers, panels, partner activities, and tutorials ((click here or on the composite image), below are some long form comments on particular aspects of this year's Design & Verification Conference (DVCon) in San Jose this past February 27 through March 1, 2012.
If the gallery doesn't open, click here.
If the video playlist doesn't open, click here.
UVM & Low Power verification come of age: In prior DVCons, the big news was the launch of new methodologies like UVM and low power verification. Both things are still a big deal, but for a different reason: the heavy attendance at the UVM tutorial, Low Power lunch, and related papers made it clear that these methodologies are being widely adopted. Hence, the attendees' questions were inspired by issues that come up in daily usage vs. past years when the Q&A was more basic and introductory in nature. Plus, as shown in this video on the paper "Creating a Complete Low Power Verification Strategy Using the Common Power Format and UVM", engineers can now create flows than span low power firmware down to assertion-based verification.
UCIS - the new standard on the block: Given that coverage and metric driven verification is now a mainstream best-practice for functional verification, the high interest in the launch of the Unified Coverage Interoperability Standard, a/k/a "UCIS" (pronounced, "ewe sys") 1.0 draft was no surprise. For more background on UCIS, please refer to this video I recorded with Cadence's representative to the Accellera UCIS committees, John Brennan.
Formal Apps: While formal analysis tools have made great strides in improving ease-of-use over the years, many engineers are still put off by formal's lingering reputation for needing a Phd in the technology to get value from it. Even worse: it's often difficult for formal users to translate their progress into terms their simulation-centric colleagues and managers can understand. Consequently, Cadence's "Team Verify" has created an "apps" approach, where we can structure a solution in a way that's familiar and/or easy for non-experts to use, and that are relatively easy for formal and formal+simulation to solve. In this video interview Product Engineer Chris Komar recaps the tutorial on this technique we gave on Thursday March 1, 2012 at DVCon. Also note that in this tutorial our partners Oski Technology and NextOp Software shared their real world case studies of the many apps they've created for their customers -- i.e. this new "apps" approach is something that's widely applicable.
Our Rubik's Cube solving robot: Speaking of formal verification "apps", we couldn't resist the opportunity to introduce our own formal verification-driven Rubik's Cube robot app. Leveraging a mechanical design by Lego Mindstorms wizard Hans Andersson, my colleagues Apurva Kalia, Suman Ray, and Manu Chopra set up the brain of the robot to be a single SVA assertion that is solved in a few seconds by Incisive Formal Verifier (IFV). (The core program is a single SVA assertion (in a nutshell, "never (solved cube)"), which IFV solves and then produces a counter example which turns out to be the optimal solution to the cube. A script translates the counter-example signals into a set of actuator commands for the robot to execute.) As you can see in this video, the demo itself was a hit, especially with human "speed cubers" who relished the competition with the machine. Of course, the demo itself enabled us to introduce the apps approach, and in general demystify formal and ABV for many attendees in a fun way.
DVCon itself: in contrast to DAC, which seems to shrink in raw attendance numbers with each passing year, DVCon showed that focused forums can still deliver. In fact, the DVCon people are claiming record attendance, which agrees with my first-hand observations. Plus: every attendee there was focused on digital design and verification, as opposed to DAC, where you just never know what domain a given attendee is coming from when they approach the booth.
Until next DVCon, may your throughput be high and your power consumption be low!
Joe Hupcey IIIOn Twitter: @jhupcey -- http://twitter.com/jhupcey
Reference LinksDVCon 2012 proceedings
DVCon 2012: Man vs Machine ... and the better Rubik's Cube solver is ...
Video Easter Egg: Incisive Formal Verifier and SVA driving a Rubik's Cube robotAccellera Unified Coverage Interoperability Standard (UCIS) Technical CommitteeDVCon 2012 Video: John Brennan on the new UCIS 1.0 announcement
DVCon 2012 Video: Interview with Rob Meyer on Low Power Verification Strategy
DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps