Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors, performance problems and unexpected generation results.
In this post, we will focus on one of the most extreme cases of unexpected generation: a constraint which is not enforced. This can happen due to problems with your code, even in a simple example such as the following:
Let’s explore a situation where the above code fails with a DUT error, and examine the full debug process – from detecting and identifying the problem to tracing its root cause.
Because the above code does a check that p.x == 100, we must conclude that if this check failed, it must be that p.x is not 100, and the constraint we gave was not enforced. Now our task is to identify the cause of failure.
We can do this by performing the following steps:
1. Open the Gen Debugger at the generation of the field. We do this as follows:
a. Issue the following command: ‘config gen –collect = ALL’. This activates the Gen Debugger, and ensures that it keeps all information. (Note: In Specman versions prior to version 11.1, the command is: ‘br gen err; config gen –del_old_dbg_info = FALSE’)
b. Issue the following command: ‘br on error’. This ensures that the Gen Debugger stops at the dut_error, so that we can determine what failed.
c. After the Gen Debugger stops, issue the following command: ‘show gen –instance p.x’ (you can specify any legal path to the relevant variable). This opens the Gen Debugger at the generation of the problematic field. This command is particularly useful when using the Gen Debugger in ‘offline’ mode, after the generation has finished. If you stop during generation (for example, on an error), the ‘gtree’ command will open the gen debugger in its current state.
In our example, the following figure illustrates the result.
Interestingly, the generated value (highlighted by the Gen Debugger in blue) shows us that the constraint was enforced.
This means that for an error to have occurred, that generated value had to have been changed later on during processing. But where? How do we find the procedural location of the change?
The good news is that we can use the Gen Debugger to help us as we try to pinpoint the location of the problem. But first we need to perform a rerun, stopping immediately after the generation.
2. Ascertain the needed values and then rerun the test as follows:
a. In the Gen Debugger, look for the Gen-Action and Connect Field Set (CFS) values. In our example (see the following figures), the Gen Action value is 2, and the CFS value is 20.
b. Reload the code and issue ‘br on gen action # cfs #’ (in our example, ‘br on gen action 2 cfs 20’), so that the test reruns and stops immediately after the generation.
c. After the run is completed, issue ‘gfinish’, which will advance to the completion of this CFS, and check the results (see the following figure). Notice that p.x. has the correct value.
At this point, the role of the Gen Debugger is over, and we need to use the source debugger. Since the problem is not in generation, we need to find out where in the procedural code this value was changed.
3. Issue the source-debugger command ‘br on change sys.p.x’ and continue. This will stop at the code which is responsible for the discrepancy (see the following figure).
Through this example, we saw that what might seem to be an ignored constraint can actually be caused by a problem elsewhere (that is, that the constraint has not been ignored.)
And in the process, we learned how to use the Gen Debugger to help locate the actual source of the problem, and we saw several aspects of the Gen Debugger, including:
· its offline and online debug capabilities (Steps 1 & 2, respectively)
· its connection to the source debugger (Step 3)
In the next post, we will see additional possible causes for the “ignored constraint” behavior, and in the process we will further examine Gen Debugger functionality.