Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e?"
Well, this is a bit of a trick question. The short answer is that if you've adopted eRM in the past, migration to UVM e will only take a few minutes. If your environment is not eRM-compliant, it will take you longer.
And now to the details. What exactly is UVM e, in comparison to native e (IEEE 1647), and to eRM? What is in UVM? And what's all the fuss about?
Let's start with a high-level view of the methodology. The UVM describes the creation of a reusable universal verification component (UVC). Each UVC defines a reusable verification environment for one protocol (AXI, PCIe, etc.) or a system (an interconnect, a bridge, etc.). The UVCs are built of agents, sequence drivers (sequencer), monitors, etc. Sounds familiar? Of course. This is eRM, and UVM is based on eRM.
So, the concept and methodology are the same. No "migration" required here.
Let's take a look at the technical details. Other than documentation, what utilities and infrastructure does the UVM package contain? UVM provides a messaging mechanism, synchronization between components, infrastructure for sequences definition and driving. Again, this should be no big news to any e user. These are things you learned in basic e training. It might seem like some terminology is not aligned. But let's look more closely. In UVM documentation or discussions you might have heard the terms "UVC," "sequencer," and "report." These are simply the UVM SV names for "eVC," "sequence driver," and "message,"; all terms you should be familiar with.
And this is why "What would it take to migrate from e to UVM e?" is a trick question. If you took Specman basic training and adopted its guidelines, you are already using UVM e. The "bread and butter" of UVM e has been part of e LRM (and Specman) for several years now.
To paraphrase the French playwright Molière, "Good heavens! For 10 years you have been using UVM without knowing it!"
So if you were simply concerned about trying out UVM, well, you already are using it!
But Cadence has more to offer. UVM e is being extended with features and methodology examples that target system verification challenges. These new capabilities are part of Cadence UVM open source, which contains the following:
To get a real feeling for what a "UVM UVC" is -- and how it differs from what you already know about verification components in e -- take a simple step: Run the Incisive Verification Builder, and create a UVM e UVC. Next, you can try to convince your colleagues and management that they should also start using UVM e.