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Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with ABVIP". Register today: http://goo.gl/rmBhh
As anyone who has worked with ARM's AMBA 4 AXITM Coherency Extensions -- a/k/a the "ACETM" protocol -- knows, there are a ton of different configuration options and operational scenarios available to the designer. Of course, this flexibility and power presents a significant verification challenge. Hence, building on the success of our ACE Universal Verification Component (UVC) Verification IP product, we are excited to announce the immediate availability of the complementary Assertion-Based Verification IP (ABVIP) for ACE. Written in standard IEEE System Verilog Assertions (SVA), this new ACE ABVIP simultaneously supports simulation-centric ABV, pure formal analysis, and mixed formal and simulation verification flows.
In this 3 minute video, R&D Product Expert Joerg Muller outlines the main capabilities of this new product -- how it offers specific configuration, run time performance, and context-sensitive work-flow advantages in the SimVision debug environment vs. competitive offerings:
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In a nutshell, this new product marries all the next generation ABVIP capabilities we introduced early this year with Cadence's deep knowledge of the ACE protocol and its many configuration options.
This product is available immediately - please contact your Cadence representative for more details, or ask us more about it via the "Contact" button at the upper RHS of this page.
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