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At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and e language-related content, or be of general relevance to Specmaniacs. Hence, if you are going to the conference, please consider printing out the following "DVCon 2013 Guide for the Specmaniac".
* Specman-centric posters at the poster session on Tuesday from 10:30-11:30am
1P.21 "Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure using Specman", presented by Meirav Nitzan of Xilinx, Inc., with co-authors Yael Kinderman and Efrat Gavish of Cadence R&D.
1P.25 "Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e", presented by Horace Chan of PMC-Sierra, Inc., with co-authors Brian Vandegriend and Deepali Joshi also of PMC-Sierra, Inc., and Corey Goss, a Solutions Architect in Cadence R&D.
The best part about the poster session is you can easily interact with the authors - asking them questions on the fly in a way that would be awkward if they were presenting the paper in a lecture format.
* The Cadence booth at the free expo on Tuesday & Wednesday Feb. 26-27, 3:30- 6:30pm each day
As always, Specman technology is directly or indirectly a cornerstone of the various demos -- UVM, Verification IP, metric-driven verification & Enterprise Manager updates, ESL & TLM updates, etc. This year we will be showcasing new automated debug technology - the Incisive Debug Analyzer - that works great with e/Specman testbenches. Even better: R&D leader Nadav Chazan will be present to walk through the tool with you and answer your questions. Of course, at a relatively small show like DVCon there is often the opportunity to digress from the primary demo(s) and discuss Specman technology updates in specific - Nadav and other members of Team Specman will be happy to give you the highlights of the new capabilities release in Specman 12.2 and more.
* Thursday morning Feb. 28 tutorial (8:30am-Noon), "Fast Track Your UVM Debug Productivity with Simulation and Acceleration"
In this comprehensive tutorial, Specman R&D's Nadav Chazan along with hardware assisted verification expert Devinder Gill will show how you can reduce debug turnaround time of class-based, software-like environments (i.e. like an e/AOP testbench). Specifically, they will show how to leverage low latency interactive debug techniques to improve debug efficiency, where the user has a much broader range of capabilities at their disposal. This includes interactive features such as forward and backward source code single-stepping, searching for arbitrary values and types, and automated go-to-cause analysis. Come prepared to take plenty of notes because Nadav and Devinder will walk through many detailed examples.
* Bonus: A free lunch on "Best Practices in Verification Planning" Wednesday Feb. 27!
On the Wednesday of DVCon Cadence is hosting an expert panel on "Best Practices in Verification Planning". Panel moderator, R&D Fellow Mike Stellfox (yes - *that* Mike Stellfox who's been with the team since Verisity days), will kickoff this important discussion on how creating and executing effective verification plans can be a challenging mix of art and science that can go sideways despite the best efforts of engineers and managers. Note that this won't be confined to RTL verification planning only -- the panel also includes experts on analog-mixed signal verification and formal analysis.
Panel discussion at DVCon 2012
We look forward to seeing you in-person soon!
The official DVCon website
Comprehensive list of Cadence-sponsored events & papers
Images from last year's show to give you an idea of what it's like, in case you have never been to a DVCon before.
DVCon 2012 video playlist
60 second highlights video from DVCon 2012
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