Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve the productivity of IBM’s project teams.
Tom Cole, verification manager for IBM’s Cores group, and I took a few minutes to reflect on verification productivity and discuss what the future holds.
Tom, can you describe the types of products your teams verify?
Our groups develop IP cores for IBM internal and external customer SoC projects. Among these are Ethernet, DDR, PCIe and HSS communications cores and memories. Our projects tend to be on the leading edge of performance and standards.
What are some of the verification challenges your teams face?
Our verification challenges fall into three major categories – mixed-signal, debug, and product-level productivity. All of our cores include PHYs, which makes mixed-signal intrinsic to their functionality, but we all know that transistor-level mixed-signal simulation is too slow for methodologies like OVM and UVM. OVM and UVM increase productivity because they reduce the test-writing effort, but they create another challenge in debugging the enormous amount of data they produce. A part of that data set - coverage - is a critical metric for us because it enables us to measure our verification progress. But it also leads to a capacity challenge due to the enormous data volume.
How are IBM and Cadence collaborating to address these challenges?
Several innovative projects are underway with Cadence to address these verification challenges. For example we have applied the metric driven verification methodology as documented in Nancy Pratt's video summary. Another project that has been running for more than a year models analog circuits with digital mixed-signal models, and shows an order of magnitude performance improvement in preliminary results. As a result, we were able to use the same models in our pre-silicon verification and in our post-silicon wafer test harness. As industry leaders, we also share knowledge derived from our collaboration through technical papers. One example is the SystemVerilog coding for performance paper delivered at DVCon 2012 and the constraint optimization paper we will deliver at DVCon 2013.
What’s next for verification productivity?
Given the complexity of verification, there are several opportunities to improve productivity. For example, a promising approach uses formal checks at the designer level to reduce the time to integrate the testbench and blocks of the design for verification. We are currently collaborating to place these static checks in our code for reuse throughout the verification cycle. This may catch unintended instabilities introduced by ECO design changes earlier in the verification process and further improve our overall verification productivity.
If you have questions for Tom or me, please post your comment and we’ll do our best to answer you quickly!
=Adam Sherer, Cadence