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Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity for verifying SoC reset. In November 2013 at CDNLive India they presented a paper detailnig the new technology they applied to reset verification and eight bugs they found during the project. We were able to catch up with Sri Ranganayakulu just after his presentation and captured this video explaining the key points in his paper.
Sri had an established process for verifying reset on his SoC. The challege he faced is one faced by many teams -- reset verification executed at gate level. Why gate level? It goes back to the IEEE 1364 Verilog Language Reference Manual (LRM). At reset, the logic values in a design can either be a 0 or 1 so a special state "X" was defined to capture this uncertainty. The LRM defined how the logic gates in Verilog could resolve these X values to known values of 0 and 1 as they occur in the hardware. Unfortunately, the LRM defined a different resolution of X values for RTL. As a result, companies like ADI simulated at gate level to match the hardware definition. But with larger SoCs, the execution of those simulations became too long. in addition, SoCs now have power-aware circuits that mimic reset functionality when they come out of power shutdown, increasing the number of reset simulations that have to occur. A change was needed.
Incisive Enterprise Simulator provides the ability to override the RTL behavior to mimic the gate behavior, resulting in up to 5X faster reset simulation. That's the attraction to "X-prop" simulation. But that is not verification. Verification requires the ability to plan and measure the reset sequences and to debug when issues are found. Sri focused on the debug aspects of X-prop verification with debug tools in SimVision to identify X values that are real reset errors from those X values that were artifically propagated in RTL. As a result, Sri found eight bugs in two projects in a shorter time than his previous approach.
In the Incisive 13.2 release, Cadence further improved this technology. The new release extends the language support for X-propagation and adds the ability to separate X values coming from power-down domains from the other two types in the previous paragraph. In addition, the Superlinting Verification App in Incisive Enterprise Verifier now generates assertions that monitor for X values in simulation. Since assertions also automatically create coverage, you now have an automated path to connect your reset verification to metric-driven verification (MDV) and your verification plan.
X-propagation in simulation is necessary to achieve performance for reset simulation. However, to get productivity for your reset verification, you need the automation from debug, verification apps, and enterprise planning and managerment.