Cadence JedAI Accelerates Automotive SoC Design for Renesas

The automotive sector is experiencing substantial changes due to revolutionary trends like CASE (connected, autonomous, shared, and electrified). Semiconductor innovations are powering these transformations. As customers demand more advanced features, such as an advanced driver assistance system (ADAS), the need for greater functionality from SoCs grows. However, this increased functionality increases verification complexity, resulting in more extended debugging periods to ensure accuracy.

Figure 1: Automotive Industry: Megatrends (Source: Renesas, 2023-04)

Also, the implementation of SoCs results in the generation of extensive unused data, which may help to improve the design quality. In other words, finding ways to reduce the debugging time to meet market demands for a shorter time-to-market is crucial. AI integration into semiconductor design is a viable solution to this problem. Renesas, a chip manufacturer, also faced this challenge and effectively utilized unused data to reduce debugging time with the help of Cadence Joint Enterprise Data and AI (JedAI). Renesas managed to save 30% of iteration time while debugging complex designs for Automotive SoC/MCU using the Cadence JedAI solution.

Optimizing Debugging Time in Complex Blocks/MCUs Designs

Fault detection in complex blocks and MCUs involves a more resource-intensive, time-consuming debugging process and routing. Renesas’s development team noticed that the vast amount of data generated from verification might play a significant role in reducing and streamlining the debugging process. This data remains unused as most of the workflow and design data is challenging to decipher and not readily available for designers to utilize. Further, they noted that the debugging time could be reduced by collecting data from the results and the ongoing operations.

How Renesas Accelerated the Automotive SoC Design

The traditional schemes involved in the automotive SoC design process use too many iterations, which makes them time-consuming and costly. To accelerate the automotive SoC design and stay ahead, Renesas needed a robust AI application that may efficiently utilize large amounts of historical data and can help to:

• Identify defects by extracting critical issues from placement and routing results
• Reduce the debugging time
• Enhance productivity
• Accelerate the high-quality chip design
• Reduce the chip’s cost to market

The Cadence JedAI platform allows engineering teams to visualize the data, uncover hidden trends, and automatically generate design improvement strategies, ultimately improving overall design performance and engineering productivity.

Cadence JedAI and Key Features Leading to its Adoption

The developers at Renesas highlighted improvement and fault detection as the main goals that can be achieved by analyzing successes and learning from failures. Renesas utilized   Chip Explorer and reinforcement learning to develop and analyze CPU and GPU improvements. However for complex blocks and MCUs, Renesas relied on agile development practices as it involves extensive data and analytics. To revolutionize the debugging process, Renesas used Cadence JedAI platform.

Figure 2: Expectations of two major AI technologies (Source: Renesas, 2023-04)

Cadence JedAI platform harnesses the vast amounts of design data generated during the verification and implementation phases of the design process. It allows engineering teams to visualize the data, uncover hidden data trends, and automatically generate design improvement strategies, leading to improved design performance and engineering productivity. Apart from this, below are key features that led Renesas to use JedAI:

• It provides a secure, highly distributed, cloud-enabled infrastructure to store and optimize vast amounts of design data, workflow data, and workload data using machine learning (ML)
• It simplifies data ingestion through Cadence data connectors and open connectors for third-party data.

Expectations and Results

Renesas used Cadence JedAI Platform to identify defects by extracting critical issues from placement and route results along with historical data, essentially creating an analysis report. This provides valuable information that can be analyzed with advanced analytic tools.  Leveraging the Cadence JedAI platform, Renesas reduced the debugging time by analyzing the outcome of each job quickly and efficiently. This scheme significantly reduced the analysis time and the number of iterations required to address violations. It enabled Renesas development teams to address all violations in a single iteration!

Figure 3: Cadence JedAI Platform: The Solution (Source: Renesas, 2023-04)

This collaboration/ new scheme helped Renesas with a 30% reduction in iteration duration. Click here to find more details about Cadence JedAI platform.

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