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So you want to build an automated testbench for your aero/defense project, eh? Luckily, there’s a solution for you. A project called CRAFT (which stands for Circuit Realization At Faster Timescales) seeks to speed the development of SoCs by providing the tools necessary to make automated testbenches faster and more easily created than ever before.
Funded by DARPA, CRAFT utilizes components from a number of different companies and institutions: UC Berkeley provided the HDL and CHISEL (Constructing Hardware In Scala Embedded Language), Cadence provided the verification workbench and VIP, and Northrop Grumman designed the Fast Fourier Transform block other IP blocks used in the design and assembly of verification environments. This culminated in Phase 1 of CRAFT: a web-based verification workbench tool called VWB.
Now, how does one build a verification workbench with VWB? First, you need to start the VWB server app, which generates a URL that you can plug into the browser of your choice to reach the tool. Once you’re there, go to the tab for a UVM testbench. Select “+” to create a new UVM testbench. Then, add your DUT to it. You can then add some Verification UVCs to the testbench—the GUI allows for UVC config and port sizing. Specify your testbench’s name, then select a structure to fill it in.
Once you’ve gotten this far, you can add some clocks to your design. VWB lets you choose monitor or driven clocks, and all you have to do to add them is drag and drop them from the clocks panel to your testbench panel—and as soon as the icon next to the clock turns green, you’re good to go.
VWB also generates a run script for you right out of the box—and it’s all compatible with SimVision, so can easily get to your existing debug tools. VWB supports all sorts of VIPs, including AMBA, MMCARD, CSI1, I2C, SPI, UART, and more.
Using the VWB results in a massive reduction in time when developing your DUT’s first environment: you can put it together in around an hour instead of in a week. Thanks to IPXACT metadata, VIP config and instantiation is much easier, and you can also do full-register tests based on that metadata. For the best results, be sure to use testbenches that run one vector at a time; any more than that, and UVM doesn’t work as well. As of this moment, testbenches created with VWB are not emulatable in hardware such as Palladium Z1 — they’re just regular UVM testbenches—but functionality on that end is planned for future updates.
To see Northrup Grumman’s presentation on this topic, check here.