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Previously unpublished data from ChipEstimate.com suggests that design activity at the 130 nm and 180 nm process nodes remains very strong, despite a recent upsurge in interest in 65 nm. This data has some interesting implications for EDA, silicon IP, and foundry providers, as well as IC design teams.
In a tech article published in the ChipEstimate.com April 7 IP Connections newsletter, I look at data gleaned from over 75,000 IC estimations run during the past five years. IP Connections is a bi-weekly newsletter that runs technical articles about system-on-chip design and provides current IP listings.
ChipEstimate.com, which is owned by Cadence, provides the InCyte Chip Estimator. This is a tool that provides a project feasibility analysis during the early stages of chip planning. It is also available as a free downloadable Starter Edition. Since users provide information about such criteria as process nodes, metal layers, power consumption, clock speed, and silicon IP usage, ChipEstimate.com is able to track high- level data about IC design trends over selected periods of time. This is aggregate data and is not user specific.
While my IP Connections article has more details, here are a few quick findings from InCyte data about chip estimations at various process nodes:
In the industry trade press, it seems that everyone is talking about 32 nm and 22 nm process nodes. That discussion should be happening – the tooling and methodology for new process nodes has to be in place before volume production can begin. But it’s easy to lose sight of the importance and relevance of higher process nodes, and to forget how strong the 130 nm-and-above nodes still are as “workhorses” for a large part of the semiconductor industry.
It is likely that many designs staying at 130 nm or above contain analog circuitry. Analog doesn’t scale as well as digital, and may not tolerate the lower voltages of lower process nodes. If 130 and 180 nm remain robust and well-supported into the future, you may see more “stacked die” implementations where the digital circuitry is placed on a 45 nm die and the analog circuitry stays at 130 nm or above. That’s a lot easier than cramming everything into a 45 nm system-on-chip. But it does require a support infrastructure for stacked die implementations and through-silicon vias.
One clear implication is that we will have many “active” silicon process nodes in the future. EDA, IP and foundry providers will have to support 180, 130, 90, 65, and 45 nm process nodes while simultaneously gearing up for 32 and 22 nm. (TSMC still supports 0.25 microns and 0.35 microns as well). This may add to the support burden for these suppliers, and make it a little more complicated for some EDA and IP vendors to decide which process nodes to target. Anything that facilitiates IP migration between process nodes will be welcome.
IP availability is a major factor in any decision to move to lower process nodes. If you do an “advanced search” for IP at ChipEstimate.com, and ask for 65 nm IP, you’ll get 477 entries (as of April 6, 2009). If you search for 45 nm IP, you’ll get 15 entries. This may be why 45 nm estimates actually declined this year – people “kicked the tires,” so to speak, and found there’s very limited IP.
Having a range of active, supported process nodes gives IC design teams
a lot of choices. There are very good reasons for moving to lower
process nodes, but the claim that “everybody else is doing it” is not
one of them.