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Magma Design Automation’s recent announcement that its Talus IC implementation suite now reads and writes the Common Power Format (CPF) is a welcome move. But the real challenge of low-power design is not a question of formats – it’s about building a cohesive ESL-to-tapeout power-aware design methodology.
Magma, an early backer of the Unified Power Format (UPF), announced Talus support for CPF April 27. The press release cited “requests from our customers” who wanted to use the “low power format of their choice.” This should put an end to arguments that only one EDA vendor (Cadence) supports CPF. (Actually, if you go the Power Forward web site, you’ll find a list of some 35 companies participating in the CPF-based Power Forward Initiative, including Azuro, Calypto, Denali, Sequence Design, and Virage Logic).
CPF and UPF (recently ratified as IEEE 1801) both allow designers to express power intent in the RTL-to-GDSII design and verification flow. I wrote many articles for EE Times in 2006 and 2007 about the development of both formats. The time has come, however, to move past the debate about formats and focus on the full scope of the low-power design problem.
CPF is currently governed by the Silicon Integration Initiative (Si2) Low Power Coalition (LPC), which consists of 12 member companies in the semiconductor, EDA and IP industries. In an SCDsource opinion piece last year, Steve Schulz, Si2 president, argued that “the time has now come to shift the debate to a larger and more important purpose.” Some of the “grand challenges” he cited include power modeling, system-level design including software, rapid what-if power optimization, and advanced design techniques such as pulsed clocks or adaptive biasing.
Embedded software plays a huge role in power savings, but little exists in terms of standards, tools or methodologies that can help programmers write power-efficient software, as I noted in a blog posting from the recent Embedded Systems Conference. In another recent posting I talked about preliminary steps towards an IP power modeling standard, which is needed because IP vendors today derive power numbers in different ways, making chip planning difficult. Low-power analog and mixed/signal design is another area in need of attention.
In my view, some of the best (and least known) work of the LPC is not really about CPF, but is about the development of “best practices” in the form of a power-aware IC design reference flow. Authors from IBM, Sequence, Broadcom and Si2 described that flow earlier this year in an SCDsource contributed article. The flow starts at the system level, which is where the potential power savings are the greatest, and tool support is most lacking. One of the difficult challenges this flow tackles is how to model power at the electronic system level.
Power intent formats are an important piece of the low-power solution. But I hope we can all agree on the broader goal – building an effective ESL-to-GDSII power-aware flow.