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At previous Design Automation Conferences, I’ve always been most interested in what EDA users have to say. One way to hear about the user experience at this year’s DAC is to attend any of five panels at the Cadence Ecosystem Partners booth (#4200, North Hall). These panels will include representatives from user companies and Cadence partners. I’ll be moderating four of those panels. Details (subject to change) are listed below.
Monday, July 27, 2:00-3:00 pm: Putting the petal to the metal on 32/28 nm design
This panel will take an in-depth look at the design and process issues that must be resolved to make the transition to 32 nm less painful and costly. It will consider such problems as the variability of smaller transistors and wires, escalating data volumes, and the complexity of denser chips. Panelists will also discuss innovations such as high-k metal gates, silicon-on-insulator, and 3D ICs. Panelists include speakers from TSMC, Texas Instruments, AMD, and Cadence.
Tuesday, July 28, 10:00-11:00 am: What is the ecosystem’s role in virtual platform/prototyping?
This panel will consider the increasing demand for high-performance platforms for pre-silicon hardware/software verification and integration. Panelists will discuss transaction-level models as a way to build such environments, and discuss trends in standardization and interoperability. Panelists include speakers from STMicroelectronics, ARM, Virtutech, and Cadence.
Tuesday, July 28, 2:00-3:00 pm: Low power – accomplishments and looking ahead
Many low-power design techniques that appeared to be on the “fringe” three years ago have become part of the mainstream today. This panel provides an opportunity to hear from the design community what has been accomplished thus far, and what lies ahead in the future. Panelists include speakers from Global Unichip, Faraday, ARM, and Cadence.
Wednesday, July 29, 1:30-2:30 pm: Implementing an open, metrics-driven verification environment
Verification productivity can be improved through a metrics-driven approach with an open environment that supports multiple standard languages, third-party IP and verification IP, and legacy methodologies. This panel will consider what technologies are available today, and how such a methodology can be achieved. Panelists include speakers from STMicroelectronics, Verilab, Magnum, and Cadence.
Wednesday, July 29, 3:00-4:00 pm: Mixed-signal verification and implementation challenges
Chip designs today require an unprecedented integration of analog and digital content, without compromising performance or size, and using technology nodes that increase vulnerability to process and electrical variation. This panel will discuss trends, challenges and customer needs related to mixed-signal design and verification. Panelists include speakers from Micron Technology, SiRF, Cambridge Analog Technologies, and Cadence.
In addition to these Ecosystem booth panels, Cadence is co-sponsoring two DAC lunch panels:
Tuesday, July 28, 11:30-1:30 pm: Are SystemC and TLM-driven design ready to replace RTL? Sponsored by Cadence, Calypto, and Forte, this panel includes speakers from these three companies as well as STMicroelectronics and HD Lab.
Wednesday, July 29, 12:30-2:00 pm: Are you ready for 32nm? Sponsored by ARM, Cadence and the Common Platform, speakers from ARM, Samsung, Cadence and IBM will discuss the industry’s first high-K metal gate offering for 32/28 nm.
No registration is needed for the Ecosystem booth panels. Information and free registration for the lunch panels is available on line.
Finally, in the official DAC program, Cadence is sponsoring this year’s User Track and Management Day. The User Track includes three days of user presentations in such areas as physical design, timing analysis, front-end design, power analysis, and analog/mixed-signal design. Management Day includes speakers from companies such as Intel, STMicroelectronics, LSI Logic, PMC-Sierra, Texas Instruments, Freescale, Global Unichip, and Infineon. Let the user’s voice be heard!