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Are SystemC and TLM-driven design ready to replace RTL? That’s the title of a Design Automation Conference lunch panel moderated by Mark Johnstone, chief technologist for Freescale Semiconductor’s Flow and Methodology Development Organization. Realizing that Johnstone probably has a unique and interesting perspective about this issue, I recently spoke with him about the advantages – and challenges – that Freescale has encountered as it moves towards SystemC and transaction-level modeling (TLM).
First, why is this topic of interest to Freescale? “We need to improve our designer productivity across the board, so we can get chips to market sooner,” Johnstone said. “It’s no longer tenable to wait for first silicon before beginning software development. We’re really taking a holistic view of ESL from early architectural development to implementation, including high-level synthesis, verification, and virtual platforms for software development.”
One big motivation is to start software development early enough so it won’t be “the long pole in the tent” when it comes to completing a project, Johnstone said. He noted that Freescale has successfully enabled early software development in a few cases, and has even delivered virtual platforms to customers for early software development. “The limiting factor is the availability and cost of development of the models, which is why I see SystemC TLM 2.0 as being very important,” he said.
Johnstone said that SystemC is in use at Freescale for early architectural exploration, as well as model creation for virtual platforms. He noted that high-level synthesis (HLS) adoption at Freescale is in its early stages. “We’re seeing a lot of benefit, and some backing, in using SystemC and high-level synthesis in architectural exploration,” he noted. “Even if you’re committed to writing RTL by hand for optimal performance, it’s nice to know you’re implementing the right architecture.”
Johnstone sees clear advantages to a TLM-driven design flow. One problem with RTL, he noted, is that it’s very difficult to reuse. Implementation details such as the number of pipeline stages are coded into the logic, and those details are very hard to change. A TLM 2.0 behavioral model is much more reusable, and can be used as “glue” between SystemC and a SystemVerilog testbench.
How is Freescale overcoming initial designer skepticism? Some Freescale design teams are adopting SystemC for behavioral modeling, and designers are seeing the advantages of that, Johnstone noted. “That’s getting them into the door thinking about SystemC as a viable language,” he said. “The next thing is to show them the value of architectural exploration. You can try hundreds of different architectures automatically to find the one that gives you the best sweet spot.” Finally, when designers consider the time-to-market advantages of HLS, they conclude it can be used for some of the blocks in their design.
At the DAC panel discussion, Johnstone said he’ll note that despite the move to RTL, there’s still a lot of custom circuit design. Similarily, he said, “the question isn’t whether SystemC will completely replace RTL, but rather whether it will become a mainstream design language.” His take: “I think the answer is yes. I think it has to.”
The lunch panel is sponsored by Cadence, Calypto and Forte. Panel members include Mike McNamara, general manager of the Cadence Systems Software Group; Tom Sandoval, Calypto CEO; Sean Dart, Forte CTO; Laurent Ducousso, ST Microelectronics; and Yutetsu Takasukasa, HD Lab. The event is free and takes place at the Moscone Convention Center in San Francisco, starting at 11:30 a.m. Tuesday July 28. Further information and registration is available on line.