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Kush Gulati is CEO of Cambridge Analog Technologies, a provider of high-performance, low-power analog and mixed-signal IP. In an interview at the recent Design Automation Conference, he talked about the challenges of analog design, modeling, and simulation, and discussed some of the approaches his company has taken. Gulati also spoke at the Cadence Ecosystem booth and participated in a panel discussion on mixed-signal design and verification.
Cambridge Analog Technologies (CAT) provides IP blocks such as A/D converters, PLLs, and DACs. The company’s PUMA (Precision Ultra Micro-power Amplification) technology cuts power consumption by 5X to 15X compared to competitive products, according to Gulati. He noted that there is digital logic inside A/D converters, and their PLLs are completely digital. Thus, the company uses a custom design methodology that can handle both analog and digital.
CAT uses both Verilog-A and Spice for modeling and simulation. “Any time we absolutely need to have the circuit working at precision at the highest performance we have targeted, we rely on Spice,” Gulati said. “Any time we need to have a functionality check, we rely on behavioral models. You can’t really go through the entire solution with Spice accuracy.”
CAT uses both the Cadence Virtuoso Spectre simulator, which is full Spice, and the Virtuoso UltraSim simulator, which is Fast Spice. Where to use one or the other? Gulati said that Spectre is used to ensure that a circuit delivers the desired performance, and that UltraSim is currently used primarily for functionality checks. But he said CAT is “adopting a more digital flow” and expects to rely more heavily on UltraSim in the future.
In the attached video clip, Gulati talks about the challenges of analog simulation. He also notes how Spectre helps with some of these challenges.
If video fails to launch click here.
A final question was as follows: If somebody buys your analog IP to integrate into an SoC, how much verification do they need to do?
“We work with customers to make sure we get information about their interfaces prior to giving them IP,” Gulati said. “Once we give them the IP, we hope they are able to take the behavioral models we provide in Verilog and Verilog-A and simulate within their flow. Also, in some cases, we provide encrypted netlists so they can simulate at the Spice level. For an RF or analog baseband chip, that’s very useful.”