Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Kush Gulati is CEO of Cambridge Analog Technologies, a provider of high-performance, low-power analog and mixed-signal IP. In an interview at the recent Design Automation Conference, he talked about the challenges of analog design, modeling, and simulation, and discussed some of the approaches his company has taken. Gulati also spoke at the Cadence Ecosystem booth and participated in a panel discussion on mixed-signal design and verification.
Cambridge Analog Technologies (CAT) provides IP blocks such as A/D converters, PLLs, and DACs. The company’s PUMA (Precision Ultra Micro-power Amplification) technology cuts power consumption by 5X to 15X compared to competitive products, according to Gulati. He noted that there is digital logic inside A/D converters, and their PLLs are completely digital. Thus, the company uses a custom design methodology that can handle both analog and digital.
CAT uses both Verilog-A and Spice for modeling and simulation. “Any time we absolutely need to have the circuit working at precision at the highest performance we have targeted, we rely on Spice,” Gulati said. “Any time we need to have a functionality check, we rely on behavioral models. You can’t really go through the entire solution with Spice accuracy.”
CAT uses both the Cadence Virtuoso Spectre simulator, which is full Spice, and the Virtuoso UltraSim simulator, which is Fast Spice. Where to use one or the other? Gulati said that Spectre is used to ensure that a circuit delivers the desired performance, and that UltraSim is currently used primarily for functionality checks. But he said CAT is “adopting a more digital flow” and expects to rely more heavily on UltraSim in the future.
In the attached video clip, Gulati talks about the challenges of analog simulation. He also notes how Spectre helps with some of these challenges.
If video fails to launch click here.
A final question was as follows: If somebody buys your analog IP to integrate into an SoC, how much verification do they need to do?
“We work with customers to make sure we get information about their interfaces prior to giving them IP,” Gulati said. “Once we give them the IP, we hope they are able to take the behavioral models we provide in Verilog and Verilog-A and simulate within their flow. Also, in some cases, we provide encrypted netlists so they can simulate at the Spice level. For an RF or analog baseband chip, that’s very useful.”