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The discussion about low-power IC design has been focused on digital implementation from RTL on down. We are beginning to move above RTL with tools and methodologies that consider power at a systems level. But what’s not so often discussed is the use of low-power design in mixed digital and analog ICs, and the impact of low power design on mixed-signal simulation.
At a low-power design panel at the Cadence Ecosystem booth at the recent Design Automation Conference, I asked how low-power design techniques affect analog circuitry. Albert Chen, field applications and marketing manager at Faraday, responded that many analog blocks have their own power rails and power supplies. He noted, however, that “we are seeing more and more analog IP that actually has low-power features as well. Let’s say there’s a three-channel DAC – it might be possible to power down one or two of those channels.”
I heard this point in a previous conversation with Koorosh Nazifi, engineering group director at Cadence. Historically, he noted, techniques such as multiple voltages and power shutdown have been implemented in the digital portions of an IC. But now there’s a trend towards the use of power shutoff (PSO) and multiple voltage levels in analog circuits, particularly in RF and wireless applications. Dynamic voltage and frequency scaling may appear in the future, but hasn’t really shown up yet for analog IP.
In a mixed digital and analog chip, low-power design techniques used on digital IP can affect neighboring analog blocks, and vice versa. This creates interesting scenarios for simulation to consider. Koorosh offered the example of a switchable digital control logic circuit that manages an analog/custom circuit such as an SRAM. When power is shut off on a digital signal that feeds into the analog circuit, the effects need to be reflected properly during mixed-signal simulation. Otherwise, debugging an X (unknown) state that could result from either the shutoff or a functional failure would become error prone and tedious.
Even for digital-only simulation, PSO is a challenge, as noted in a recent Cadence whitepaper on low-power verification. During shutoff, the simulator models data corruption internal to the power domain by setting all the internal values to Xs. This can invalidate unclocked assertions, prevent coverage events from triggering, and complicate scoreboards.
In a mixed digital and analog simulation, logical (digital) pins are interacting with electrical (analog) pins. Digital pins know only about 0, 1, X, and Z. Analog pins understand continuous values. Somehow digital logic levels must be translated into analog voltage levels. In the Cadence Virtuoso AMS Designer product, this can be done through automatically inserted virtual blocks called Connect Modules.
But what do we do if a power shutoff forces an X output from a digital block, and the digital block is interacting with an analog block? If an analog signal’s source can be traced to a digital signal that has a Common Power Format (CPF) definition, AMS Designer can automatically insert a “Power Smart” Connect Module that can distinguish between an X resulting from a functional error and an X resulting from PSO. The module can also back-trace digital drivers to get power domain and state information, and can perform a digital-to-analog value conversion based on this information.
What about analog blocks that use PSO or multiple voltage levels? You might have to insert isolation logic or level shifters, and if you do insert digital logic, this can be checked with a formal tool such as Encounter Conformal Low Power. But analog circuitry will need to be checked with Spice.
These are the kinds of challenges we need to start thinking about in the low-power design arena. To do so, we need to start thinking out of the digital “box” and remember that it’s the power consumption of the entire design, including all the analog components, that really matters.