Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Running full-chip, mixed-signal simulations with sufficient accuracy and speed is a huge challenge for system-on-chip (SoC) designers. But engineers at SiRF, a provider of GPS chipsets and subsystems, have been able to do so, according to Marcelo Silva, verification engineer. In an interview at the Design Automation Conference, Silva talked about SiRF’s use of Verilog-AMS, real value modeling, Spice, and fast Spice for analog/mixed-signal simulation.
Prior to the interview, Silva spoke at a panel discussion on mixed-signal design and verification at the Cadence Ecosystem booth. Here, he talked about the challenge of running simulations that combine large amounts of digital circuitry running at slow clock speeds with analog/RF IP running at perhaps 3 GHz. Maintaining sufficient accuracy on the analog side while keeping run-times reasonable is a huge challenge, he said. Silva discussed an approach that uses verification planning, a single testbench driven by digital verification engineers, Verilog-AMS at the block and chip level, and real value modeling with the Verilog-AMS wreal construct.
In the interview, Silva noted that SiRF designs its own analog blocks, and thus has both analog and digital design systems and engineers. The company uses the Cadence Virtuoso system for custom design, Virtuoso AMS Designer for mixed/signal verification, and the Incisive Plan-to-Closure methodology for digital verification.
In the attached video clip, Silva talks about how SiRF models analog blocks, and discusses how the company uses Verilog-AMS, full Spice with Virtuoso Spectre, fast Spice with Virtuoso UltraSim, and wreal modeling in order to verify its mixed-signal SoCs.
If video fails to launch click here.
Still, there’s room for progress. Silva noted he’d like to see better handling of voltage scaling in mixed-signal simulation. He would also like to see an analog/mixed-signal version of SystemVerilog, analogous to Verilog-AMS. That would help with randomization and coverage in mixed-signal test generation, he noted.
Silva also spoke to a deeper challenge at the panel – communications between design teams. “Usually the analog and digital guys never talk to one another,” he said. “In our flow, it has to be integrated.”