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One way to gauge the quality of high-level synthesis is to run it on an existing design, and compare the synthesized RTL with the previously hand-generated RTL in power, performance and area. The Industrial Technology Research Institute (ITRI), a Taiwanese research center, recently did just that with the Cadence C-to-Silicon Compiler, as described by ITRI design engineer Jen-Chieh Yeh at the Design Automation Conference.
In a presentation at the Cadence Ecosystem booth, Yeh described the use of high-level synthesis with a control-dominated multimedia SoC. He noted that high-level synthesis saved 8 engineer-months out of a 12-month development cycle. He also noted that synthesized RTL code maintained the original critical path delay, reduced gate count by around 14 percent, and reduced average power consumption by around 8 percent compared to hand-crafted RTL.
Following his presentation, Yeh answered a few additional questions about ITRI’s interest in high-level synthesis and about this experiment with C-to-Silicon Compiler.
Q: Is ITRI adopting an ESL design flow? Why?
A: We have taped out some SoC chips. We want to model virtual platforms and compare the results in a very detailed way. We use the real chip and compare it to the virtual platform in timing and behavior, and we can get near to 90 percent timing accuracy in the virtual platform.
In the first phase, we just prove that timing and behavior are similar to the real design. In the second stage, we use the virtual platform to do architectural or performance improvements. For example, the multimedia SoC might be decoding software, and then we find somewhere that a wait state is redundant. We can explore this on a virtual platform, but cannot find it on an FPGA or in the real silicon. We can make software modifications and perhaps get a 15 percent performance improvement with the virtual platform.
Q: What’s your interest in using high-level synthesis?
A: We are trying to use SystemC to model our IP, and then use high-level synthesis to get the RTL. Coding in RTL is easy for the hardware design engineer, but when we verify the design, it takes a lot of time. Sometimes we want to modify something, but RTL code is very difficult to modify. We can easily modify designs and get better designs with C++.
We also have a virtual platform for IP modeling, and we hope we can reuse the SystemC model to generate RTL.
Q: How long did it take to create the SystemC model that went into high-level synthesis?
A: Nearly two months. The first month, Cadence provided us with synthesizable coding guidelines. The second month, we were coding the design.
Q: What constraints did you give the C-to-Silicon Compiler?
A: The timing constraint was very clear – we needed to get the same performance. We did not give power or area constraints.
Q: How did the synthesized RTL code compare to the hand-crafted RTL?
A: For the generated RTL, code size was larger, but this is not very important. Quality of results was better, and that is very important. We want high-level synthesis to optimize timing, area and power better than hand-crafted RTL.
Q: What still remains to be done?
A: We have to generate RTL that is equivalent to the SystemC. I think equivalence checking is a good way to make sure the high-level synthesis tool generates an RTL netlist that is equivalent to SystemC.
We have a high-level model that we just keep in SystemC, and we can get high-coverage verification in a very short period of time. But we also have an RTL verification environment, and we have to guarantee the same coverage. We are investigating how to get high code coverage, functional coverage, and assertion coverage at the SystemC level.