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Most of the discussion about low-power design has centered around the RTL-to-GDSII flow for digital ICs. But the real problem is much broader, according to panelists from AMD, Sonics, Wipro, and Cadence at the recent Power Forward Initiative (PFI) Low-Power Design Summit Oct. 20.
Entitled “The Low-Power Evolution: Challenges and Opportunities,” the panel was chartered to take a high-level view of how low power design is changing and how it impacts product development. As moderator, I noticed (but wasn’t surprised) that panelists said very little about the RTL-to-GDSII digital IC design flow. Instead, the focus was on early power estimation, analog/mixed-signal design, embedded software, packaging, and other areas where automation is still lacking. Some interesting comments are noted below.
SoC integration complexity and power
“The SoC integration problem is growing as we add more and more cores together, we have more and more power domains, more and more clock domains, and a higher level of problems to solve,” said Scott Evans, director of software at IC interconnect provider Sonics. “CPF [Common Power Format] allows you to describe what you’re trying to build, but then it’s even easier to add more complexity to your design.”
Ron Burns, general manager for semiconductor and systems solutions at design services firm Wipro, said his biggest concern with respect to low power is analog/mixed signal design. He noted that his company is designing an increasing number of systems-on-chip (SoCs) with analog interfaces. “What we’ve found is that digital is performing well even down to below 40 nm,” he said. “What we’re concerned about now is making sure we have the right flow for analog and digital.” He said he’d like to see the same IP library format across both domains.
“We’ve done a fairly good job of automation and risk reduction in the digital portion of the design, and we’re pushing forward into analog/mixed-signal and starting to address packaging alternatives,” noted Steve Carlson, vice president of solutions marketing at Cadence.
Ron Burns (Wipro), Steve Presant (AMD), Scott Evans (Sonics), and Steve Carlson (Cadence) discuss low power at the PFI Summit (left to right).
Embedded software and operating systems
“Being able to take advantage of power at the software level is a huge factor in terms of being able to save power,” said Evans. “Providing interaction with the hardware so software can control it better is certainly a place that needs a lot more work and a lot more automation.”
There’s a “huge opportunity” to take a more holistic approach towards estimating hardware and software together, said Steve Presant, fellow at AMD. He suggested “an environment where an application profile describes power, and an OS considers that and interacts with the hardware.”
The link to packaging
Wipro’s Burns cited a case in which his company designed a graphics accelerator IC while separately working with a packaging partner. “The only way to transfer information from the design database to the packaging house was through Excel files,” he said. “We don’t yet see a seamless way to interoperate between packaging and design. The reality is that the packaging companies use custom internal tools, and interoperability just isn’t possible.”
“It is critical for us to be able to estimate power and performance at very early stages,” said AMD’s Presant. Today, he said, “we do a lot of work based on Excel and we use a spreadsheet to make estimates based on area approximations and voltage and frequency estimates. It’s very crude. I think the future is transaction-level power approximations, so if you know that a certain transaction or activity carries a certain amount of energy with it, you can approximate power that way.”
As an IP provider, Evans said, Sonics needs its IP models to work with models from other sources. “We need some type of standardization for power estimation for models, so that when you plug in the models you know what you’re looking at and you can provide those early estimates,” he said.
Carlson talked about how emulation can provide a dynamic power analysis, help users evaluate the impact of software, and make it possible to select a “window” of operations for detailed analysis.
It’s the whole product
I started to make a point that I’ll bring out a little more here. The end consumer of an electronics product does not care how much power an IC dissipates. The consumer cares how long the battery life is, what it will cost to run the device, or what the environmental impact is. Low power isn’t just about digital chips – it’s about the entire system, with its analog components, packages, printed circuit boards, wiring, enclosures, fans, heat sinks, and software. With the help of the Common Power Format (CPF) and some good tools, we have made great progress in automating the low-power design flow for digital ICs. But as PFI Summit panelists noted, the time has come to take a broader look at low-power design.