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The 32/28 nm Common Platform high-k metal gate (HKMG) technology is “ready and open for business,” according to the title of a breakfast panel at the ARM Techcon3 conference Oct. 22. Panelists from IBM, ARM and Cadence talked about the benefits of HKMG, the requirements it places on the design flow, and the deep and early collaboration that made a supporting ecosystem with libraries and tools possible.
All of the panelists talked about the Common Platform/ARM/Cadence collaboration, which began in 2008 just a few months after the Common Platform started its process development work. Starting that early is very unusual, according to Jaya Jagannathan, director of semiconductor technology business development and marketing for IBM’s System and Technology group.
Jaya Jagannathan (IBM), Rob Aitken (ARM), and Vassilios Gerousis (Cadence) discuss the Common Platform 32 nm HKMG technology (left to right).
HKMG, introduced by the Common Platform at 32 nm, promises significant power and performance advantages. The main benefit of HKMG, according to Jagannathan, is that it allows the scaling of gate lengths to continue. This had almost stopped at 90 nm, he said, because gate oxides were only a few angstroms – and atoms – in width. But HKMG, which uses thicker materials, allows scaling to resume. Further, he said, HKMG allows the “densest SRAM in the industry at 32 nm.”
Jagannathan also said that the 32/28 nm process uses a “gate first” approach in which gates are processed towards the beginning of the process flow. This, he said, allows a 50 percent scaling from one generation to another, while minimizing design restrictions and avoiding the addition of complex process steps. “Based on all the work we’ve done jointly, I can tell you that we can achieve the gate density we promised, we can achieve the performance we promised, and we can achieve the simplicity that we promised with gate first,” he said.
Why 32/28 nm? 32 nm is the main process node, but it’s designed so that a 10 percent optical shrink will enable the half-node of 28 nm. Today, Jagannathan said, a 32 nm low-power (LP) process design kit (PDK) is available in a beta release, and a 28 nm LP PDK is available in an alpha release. IBM has been providing multi-project wafers (MPWs) to customers and partners including ARM and Cadence.
Rob Aitken, R&D fellow at ARM, noted that a physical IP library for the 32/28 nm HKMG process is available for download now. It includes 12 memory compilers, logic libraries, and new multi-channel libraries. The multi-channel libraries make it possible to reduce leakage by using cells that have slightly longer gate lengths. It’s an alternative to the use of high voltage-threshold cells, which can reduce performance.
“The HKMG process is really quite different from previous processes,” Aitken noted. As such, ARM and the Common Platform worked together on design rules, manufacturability, and the library itself. Aitken said ARM has had five tapeouts with the Common Platform 32 nm process, and one 28 nm tapeout. These test chips made it possible to demonstrate early collaboration and to work on design rules.
ARM also used the test chips to run feasibility studies. Engineers found that the 32 nm LP process is able to attain frequencies in the GHz range on critical paths at a nominal operating point.
Vassilios Gerousis, senior architect at Cadence, discussed two 32 nm test chips that Cadence developed with IBM, as described in a previous blog. One let Cadence develop a CMP model, and showed that the 32 nm process has less relative copper loss than 45 nm but higher variability. Another showed that the random variation is large compared to stress, which is a systematic variation. Results may change as the process matures, he noted.
Gerousis noted that Cadence has focused on several areas related to 32 nm, including advanced layout rules, a high-frequency router option to NanoRoute, manufacturing awareness, and the ability to handle large designs. “32 nm is really a breakthrough in terms of layout rules. The number of layout rules is tremendous, and the impact on layout tools is also large,” he noted. NanoRoute is “100 percent compatible” with these layout rules, he said, and the Cadence Virtuoso Space-Based Router supports 32/28 nm layout rules as well. To help with random variations, Cadence is supporting statistical design for timing, signal integrity and leakage.
Panel moderator Ana Molnar Hunter, vice president of foundry for Samsung Semiconductor, closed the panel by stating that “we’re seeing tremendous customer interest in this technology because of the advantages HKMG brings to customers. There’s a lot of excitement and a lot of built-up demand.” Indeed, a full room for an early morning breakfast panel is itself a sign of interest. Designing in a new process node is never easy, but it appears that those who want to move forward will find plenty of ecosystem support.