Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
At a discussion at the ICCAD conference last week, EDA notables Jim Hogan and Paul McLellan talked about “what EDA needs to change for 2020 success.” One topic they emphasized is “software signoff,” and they encouraged those present – mostly bloggers – to go forth and write and tweet and blog about it. It’s an interesting concept, but I think it raises a number of questions, as listed below.
1. What is software signoff? A GDSII file is “software,” as is an application program written for an off-the-shelf microprocessor, so we have to clearly define what “software” we are talking about. Hogan, a former Cadence executive fellow and current private investor, defined software signoff as “signoff from behavior to an implementation in embedded software and/or a hardware implementation fabric.” Both he and McLellan, author of the EDA Graffiti blog, indicated they were talking about behavioral C/C++ code, not SystemC.
However, the word “behavioral” can mean many different things. Is it purely algorthmic, or does it define an architecture? What exactly is signed off, by whom, and to whom? How is existing silicon IP handled? Are constraints provided? In sum, what are the deliverables for software signoff?
2. What are the advantages and tradeoffs? The idea is appealing – you write some code in C/C++, and turn it over to machines and/or people who will convert it into a programmed system on chip (SoC) or FPGA. But what are the implications for performance, power, area, and unit cost?
3. What are the tooling requirements? Either the algorithm-to-silicon path will need to be automated, or you’ll be turning the behavioral software specification over to a hardware design team using traditional methodologies, in which case you’re moving work to a different location rather than actually reducing it. There has been tremendous progress in high-level synthesis with tools like the Cadence C-to-Silicon Compiler, but no tool automates the entire flow from algorithms to GDSII. Software signoff will also require some really good estimation, prototyping and profiling tools.
4. What are the silicon requirements? It seems to me software signoff will work best with some kind of predefined fabric, such as an FPGA, where someone has already taken care of issues relating to manufacturability, yield, and process variability. Otherwise, these will need to be dealt with.
5. What about analog integration? Hogan commented that analog design is inherently “algorithmic.” True, but algorithm-to-transistor synthesis has not worked very well in the analog world. Nearly all SoCs going forward will be mixed-signal, and somebody has to design and integrate the analog portions.
6. How is verification handled? Somebody needs to verify that the implementation matches the spec, is functionally correct, and meets timing and power requirements. Who does that and how?
7. Where will software signoff make sense…and not? I don’t think software signoff will be used for applications that need highly optimized performance, power or area, or those that need a very low unit cost. It could work well, however, for people want to accelerate applications using an FPGA or hardware acceleration platform, but who don’t want to, or can’t, do hardware design themselves. (I am assuming that software signoff involves some custom hardware creation or reconfiguration – otherwise, you’re just writing software for off-the-shelf hardware).
In conclusion, I think “software signoff” is one way that some people will create embedded applications. But there will be other methodologies as well. Right now, the most logical move is from RTL to a SystemC transaction-level modeling (TLM) based design and verification flow, with high-level synthesis and virtual platforms. That flow is available today.
I really have only one prediction about EDA in 2020 – that one size will not fit all.
Note: Slides from the Hogan-McLellan presentation are available at the Si2 web site. Other blogs commenting on the discussion are listed at http://leepr.com/Home.html.