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Formal verification can serve as the primary verification methodology for an entire ASIC if it meets the right criteria, according to Yogesh Bhagwat, technical lead at Cisco. At the recent CDNLive! Silicon Valley, Bhagwat described the verification of a DDR3 command buffer ASIC using the Cadence Incisive Formal Verifier (IFV).
Bhagwat demonstrated that formal verification can take the lead when ASICs are well specified, and don’t have too much sequential depth. In his presentation, he talked about the difficulty of stimulus generation and coverage for his memory expander ASIC, given the large number of legal configurations. He noted that formal verification requires no stimulus generation, and that cover statements provide coverage information. With IFV, Bhagwat attained 100 percent functional coverage on the cover points that were specified, and the chip proved defect-free in the lab.
In this video clip from an interview following his presentation, Bhagwat noted why formal was a good choice for his memory expander ASIC, why simulation would have been challenging, and how simulation was used to augment formal verification.
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Relying primarily on formal verification, Bhagwat said, greatly reduced the verification effort, and provided “the peace of mind you get by knowing all of the possible cases have been checked.” To write properties, he started with an English language description of the chip and its valid configurations, and developed SystemVerilog assertions from that. Cover points allowed his team to evaluate coverage. Debugging was primarily done with waveforms generated from counter-examples, providing a familiar debug environment for verification engineers.
Bhagwat’s advice: “Evaluate your modules and look at the modules that are best specified, and see how complex they are. If they are amenable to formal verification, then it may turn out to be the fastest way to verify that particular module.”