Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Can EDA vendors parallelize millions of lines of legacy code, or do they need to rewrite everything in order to run on multicore and many-core platforms? In a Dec. 8 interview for Intel Software Network TV, Tom Spyrou, distinguished engineer at Cadence, described how legacy code can be parallelized for 4 or 8 processors. But scaling beyond that will require some significant re-coding, he said.
Intel Software Network TV runs a weekly Parallel Programming Talk at 8 am Tuesday Pacific time. In addition to watching on line, you can listen to it live or download it from BlogTalk Radio. Hosts are Aaron Tersteeg, Intel multicore community manager, and Clay Breshears, master of the parallel universe (they have some interesting titles at Intel). The program looks like a great resource for parallel programmers.
As I noted in a previous blog, Tom has been working to parallelize the Encounter Digital Implementation System for the past three years. He is active in the parallel programming community, and he writes a blog for the Intel Software Network.
Why write the blog, and participate in the interview? “Intel has a large program in place to educate developers and fund others to educate developers worldwide in parallel programming,” Tom said. “Since we have made a lot of progress in parallel computing at Cadence and have been able to retrofit existing applications to some degree, this is interesting for Intel and their software community.”
In the Dec. 8 Intel TV interview, Tom noted that large legacy software applications don’t have to be rewritten to run on today’s multicore processors. The trick, he said, is to find pieces of code that are amenable to parallelization without rewriting the whole application. With luck, you can identify pieces that take up 30% or 40% of the run time and show a big performance increase in a short period of time. After that it gets much harder, and as described in Amdahl’s Law, any remaining code that is not parallelized will greatly limit the overall performance increase.
While you can “buy yourself some time” using tricks and techniques to parallelize legacy code, if you want to scale much beyond 8 processors you will have to rethink applications, Tom said. With many-core processors, Amdahl’s Law will become a severe bottleneck if there is any serial code at all.
Tom also made the following points in the 20-minute interview:
EDA software is some of the most complex in the world, so if it can be parallelized, other applications can. Cadence software helps Intel and other companies build multicore chips – so it’s only fitting that Cadence’s experience with parallel programming should help Intel’s developer community make use of those chips.