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Located a block away from the University of California at Berkeley, the Cadence Research Laboratories provides a unique environment for EDA innovation. But what really goes on there, who works there, and what is the place like? To find out, I recently made the one-hour trip from my Cadence San Jose office to have a look for myself.
I don’t know what I was expecting in terms of facilities, but what I found was impressive. The lab occupies two stories high in a building on Shattuck Avenue, with a great view of the San Francisco Bay and the Berkeley hills. It has a number of offices, conference rooms, an auditorium, a library, a lunchroom, server farm, and a reception area featuring several translucent walls filled with artistic circuit diagrams (shown in photo to the right with Andreas Kuehlmann, director of Cadence Research Labs).
Nice facility, but what’s it all about? “The idea of the lab was really to have a technology pipeline that starts in early research, connects to the academic world, and makes an impact on current and future products,” Andreas told me. “I think the uniqueness of the lab is that we are a dedicated research facility, and that we do not have product responsibility.”
“Other organizations doing research are more directly tied to product development,” said Ken McMillan, Cadence fellow and a veteran of the labs since 1994. “Here, we can be a little more independent of software development cycles, so we can think more long-term and out of the box.”
The spectrum of research at the lab is very broad. “Having an entity that is very compact in terms of team size, that covers the entire spectrum of products from the system-level all the way down to DFM, gives you a unique opportunity to cross boundaries and work on different time horizons,” Andreas said.
The lab was fairly quiet the day I was there, but even so, I interrupted some people at lunch long enough to pose for a picture in the library. In addition to a dozen or so resident researchers, the lab also provides temporary offices for other Cadence R&D personnel and executives, brings in students on internships, and enjoys frequent visits from professors and industry experts. “The team is really very diverse, coming pretty much from all over the world,” Andreas said.
Results are what really counts, and since its inception in 1994 (in a different location), research at the labs has turned into many successful products and product features. For example, the lab has been doing research in formal verification for many years, producing some of the verification engines used in tools such as Cadence Incisive Enterprise Verifier.
The Cadence C-to-Silicon Compiler had its origins at Cadence Research Labs. Researchers have also done a lot of work with Cadence Encounter RTL Compiler, where they have made contributions in sequential optimization, retiming, advanced clock gating, and physical-driven logic optimization. In the analog/custom area, lab researchers have developed technology for circuit simulation and compact modeling.
Andreas said that current research activities include system-level modeling with TLM (transaction-level modeling) and system power modeling, formal and simulation-based verification, logic and physical synthesis, and circuit modeling and simulation. What he’s most excited about, however, is research in parallel programming for EDA applications. “I think a lot of EDA will be re-invented, and there are lots of opportunities to do new things we were not able to do before,” Andreas said. “If people are saying EDA is solved, I whole-heartedly disagree with that. There are lots of new challenges.”
Part two of this blog entry will include short video interviews with three Cadence Research Labs researchers – Ken McMillan, Joel Phillips, and Yoshi Watanabe.
Hey this is one post I was really waiting for. I always wanted to know what really happens at Cadence Research Labs. Thanks Richards. Waiting for more posts in this series.