Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Applying restricted design rules (RDRs) to conventional design styles won’t produce good results, says Scott Becker, CEO of Tela Innovations. A better approach, he says, is to start with a restricted design style with regular layout patterns.
There’s been a lot of recent discussion about restricted design rules (RDRs) and their ability to help achieve process scaling. In Tela Innovations’ experience, restricting design rules not only achieves higher yields, but will be required for scaling to 22 nm and below. The resistance of the design community to RDRs is causing an undue burden to be placed on process development, potentially delaying the availability of these advanced process nodes.
Our observation, however, is that designers frequently take RDRs and attempt to apply them to conventional design styles. Applying RDRs to a conventional design style will yield marginal results. An alternative would be to start with a design style that is more suited for the manufacturing equipment.
It’s well known that regular structures, such as memories, are more manufacturable than the random layout structures currently used in logic design. Typically, memory manufacturers are able to get more out of the processing equipment than logic manufacturers. As the geometries reach the ultimate capability of the lithography equipment, distortions occur at bends, and in extreme cases can cause shorts or opens.
For a given piece of lithography equipment, the highest resolution is reached when printing straight lines. For example, a typical 193nm 1.2NA immersion system has a straight line capability around 45 nm, whereas the same piece of equipment is limited to around 60 nm for a line printed with bends. From a lithography point of view, if a design were constructed of straight lines, the lithography equipment would have more margin and resolution.
We have demonstrated this phenomenon in 45 nm silicon. Our test results show that an environment of straight lines produces transistors that have much tighter critical dimension (CD) control (within die and across the wafer) than transistors that reside in a 2D (bent or random) poly environment. This results in an improvement in source/drain leakage power. In our test silicon, we see a 47% reduction in leakage current due to the restricted poly environment.
Clearly, a regular design style is favored by the manufacturing process, and straight lines are the ultimate design for a lithography system. But the million dollar question remains -- can a design that is geared for the manufacturing process be implemented in a cost-effective way? The current perception in the design community is “No!” This results in demands back to the manufacturing process community to get rid of RDRs. But Tela has demonstrated that competitive area and performance can be achieved with a manufacturing-optimized set of design rules.
Depending upon the lithography capability, you can choose to limit which layers are implemented in a restricted design style. For example, products that are implemented in process geometries larger than 22 nm should utilize a restricted design style for the poly layer only. For process technologies at or below 22 nm, we see advantages to applying a restricted design style to metal layers as well.
Furthermore, cost is a function of area and parametric yield (performance and power). Competitive area and performance must be benchmarked at a block level. In our customer engagements we start by optimizing standard cells in a restricted design style. In every case we have been able to achieve equal or better cell areas compared to the original layouts.
In an unrestricted design style, designers typically bend the poly and diffusion layers in order to use them as interconnect. In our restricted design style, we eliminate bends in poly and hence avoid the use of this layer as interconnect. This forces these connections to the metal 2 level. The use of metal 2 can raise concerns for route utilization, but what we have seen in a large number of designs at 65 nm and below is that the sparse use of metal 2 in the cells has virtually no impact on route utilization and block-level area or performance. The net result is a more manufacturable design with equal or better area and performance.
The industry has lived in a world where there is complete flexibility in how we assemble the structures that make up our designs. As with most paradigms, there is a strong resistance to change. We are reaching the limits of our lithography equipment, thus requiring new design methodologies. Clearly, very regular patterns designed from straight lines are better for the manufacturing process. Designing in a restricted design environment is difficult and requires a different mind set, but we have proven that designs can be implemented with these restrictions, and we can still achieve compelling results.