Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Last month the SOI
Industry Consortium announced a "Ready
for SOI Technology" program with initial offerings of silicon-on-insulator
IP from ARM, IBM and Cadence. Since interest in SOI appears to be growing for
advanced process nodes, I thought it would be a good time to look at what
"ready for SOI" means with respect to IP, tools and people.
Last year I wrote a blog
that discussed the power advantages of SOI, so I won't repeat the details here,
except to note that the impetus for SOI seems to be shifting from high
performance to low power. While SOI claims to provide a performance improvement
of up to 30 percent versus bulk CMOS, it can also provide a power reduction of
up to 40 percent at an equivalent level of performance. Thus, the SOI
Consortium sees an opening to bring SOI, already successful in the server and
gaming markets, into new marketplaces.
But first, there must be an infrastructure that supports
SOI, and it must have three elements.
"SOI Ready" Libraries
We're assuming for the sake of this discussion that an SOI
foundry process is available (and it is - from IBM). Like any new process, SOI
requires IP, starting with standard cells, I/Os, and memories. For some time ARM
has offered such libraries for the 45 nm IBM SOI process - in fact, Cadence validated
the libraries last year. What's new is that the ChipEstimate.com site now
has an SOI portal that lists
"SOI ready" IP, including ARM standard cell libraries. Here you will also find:
So what makes IP "SOI ready?" Like any hard IP, it must
follow the process rules in the process design kit (PDK). There are a few
things that are different from bulk CMOS. For instance, SOI transistors have
higher drive currents, making it possible to use smaller transistors.
What concerns most novice SOI designers, however, is
modeling the history effect. Because of the floating body
transistor effect, the same transistor will switch differently depending on
recent switching activity. The good news is that this is handled at the library
level and is basically invisible to designers. One thing that's a little
different is that you will have two timing libraries for each process, voltage
and temperature (PVT) corner - Max-SOI where slower delays are needed, Min-SOI
where longer delays are needed.
"SOI Ready" EDA Tools
Timing and signal-integrity tools need to work with the two
libraries mentioned above. Timing accuracy is the same as for bulk CMOS, with
minimal flow impact. Signal integrity analysis for SOI is a bit more complex.
Because of the history effect, the floating body can have a large swing, and
this can cause some uncertainty in drivers and receivers. A signal integrity
tool must be able to model the history effect in the presence of noisy nets. The
Digital Implementation System offers these capabilities.
"SOI Ready" People
Preparing designers for SOI is not difficult - in fact, advocates
say, a good start takes only a few hours.
The SOI Consortium is offering a Jump Start Training session
Wednesday, April 28 at Cadence San Jose headquarters, from 9:30 am until 3:00
pm Pacific. It can also be accessed as a live and recorded webcast. Registration
is free and open to anyone.
"In about four hours, we can put forward the information
that designers need to know to get started in SOI," said Jeff Wolf, director of
membership development at the SOI Consortium. The fact that this can be done in
four hours (plus lunch) "dispels concerns in the industry that people have to
have experience in SOI to design successfully in SOI. That's not the case,"
If you're curious about SOI, come by or log on!