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One of the most interesting features of the Cadence Open Integration
Platform, introduced May 5 at the CDNLive!
EMEA conference, is that it offers a new view of how silicon IP should be
provided. In fact, the term "silicon IP" may have to be revised, because we're
now talking about an "IP stack" that includes device driver software along with
a verification environment. Why would SoC integrators want such a stack? I'll
explain in a moment, but let's set some context first.
The recent EDA360 vision
paper notes that many design teams are focusing on IP integration as much
as, or more than, design creation. The traditional EDA market focuses on design
creators. Integrators have their own needs, but except for a few point tools,
those needs have rarely been directly addressed. The Open Integration Platform is
a combination of tools, services, and IP aimed at supporting SoC integration.
The end goal is what the EDA360 paper calls SoC Realization, which is the
successful completion of an SoC ready for system integration.
A Look at the Open
The diagram below gives a quick overview of the Open
Integration Platform. It starts with an Integration Design Environment, which
includes a combination of Cadence design and verification tools selected by the
customer. Tools such as the Cadence
Chip Planning System will especially appeal to integrators. The platform is
built on open standards, and internal and third-party tools can be added to the
Integration-optimized IP, in the form of the "stacks" I'll
discuss in a moment, will be provided by Cadence in conjunction with its IP
partners. By working with partners and internal resources, Cadence will
assemble IP blocks and drivers into IP stacks and subsystems, run compliance
tests, and ensure quality and ease of integration. Cadence currently has an
IP (VIP) business, and VIP is part of the IP stacks.
For customers with special requirements, Cadence services
teams will help identify IP offerings and build customized design environments
that support specific integration needs. Finally, optimized design data will be
output to a foundry or ASIC provider.
The IP Stack
A view of an IP stack is shown below. It includes a driver,
controller, physical components (hard macros), a verification environment, and
design constraints. The first IP stack introduced by Cadence is a USB 3.0
solution that includes a configured host or device controller, PHY, VIP, and
driver. Over time, Cadence will assemble IP stacks into subsystems, such as a
high-speed I/O subsystem.
SuperSpeed USB 3.0 IP stack
So why include the driver? Consider how drivers are
typically developed. Normally the IP is built first and the driver is tacked on
later, usually by someone with little knowledge of the hardware, or perhaps by
a hardware person with little understanding of the OS. The result may be a very
expensive, custom driver development effort. Conversely, system integrators may
purchase a generic driver that doesn't support the differentiating capabilities
of the hardware.
Drivers are important because they allow the OS and the end
applications to manage system hardware. Thus, they should accurately represent
the capabilities of the hardware. That's especially true if the hardware is
reconfigurable. It would be great if an application could dynamically invoke
exactly the hardware resources it needs.
Design and verification constraints are also an important
part of the IP stack. Without an understanding of those constraints, the
integration task will be much more difficult.
There aren't many genuinely new ideas in EDA and IP, but I
think the IP stack is one of them. It will be interesting to see how it impacts
the SoC design ecosystem.