Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
There's a lot of interest in 3D ICs these days, but there
are many challenges to solve before 3D IC design can move into the mainstream.
One challenge is the establishment of standards for design, modeling, and
manufacturability. But the starting point is likely to be something even
simpler - a dictionary that defines a common taxonomy for 3D ICs.
If we're going to talk about a new technology, we have to
have some agreement on what we're talking about. What, exactly, is a 3D IC? Ask
a dozen people and you might get a dozen different answers. Some people might
say, "3D ICs have been around forever - we used to call them MCMs [multichip
modules]." Others might define 3D ICs strictly in terms of through-silicon vias
(TSVs), which is a new technology. When people talk about "3D ICs" these days,
I generally assume they are referring to heterogeneous stacked die (more than
just memory) with TSVs through active layers. But that's just a presumption -
there's no standard definition.
Many other commonly-used terms lack standard definitions.
This includes system-in-package (SiP), package-on-package (PoP), MCM, TSV,
interposer, and others.
Dictionary is First Step
Last fall, the Silicon Integration Initiative (Si2) and the Global Semiconductor Alliance (GSA) held a workshop to define requirements for 3D
IC design flow interoperability standards. "The first item that resonated with
everybody is to come up with a dictionary," said Sumit Dasgupta, senior vice
president of engineering at Si2. "Once we have a dictionary, we can at least
have a taxonomy where we can exchange the same information. Right now, it's
like four blind men trying to describe an elephant."
Workshop presentations mentioned other possible standards
activities, including updates to APIs and databases such as OpenAccess; new
standard interfaces for thermal and mechanical stress engines; a new standard
for expressing thermal constraints; and 3D interface standards for package
design systems. Presentations also discussed the technology and design
challenges behind 3D ICs. Presentations from 19 organizations and companies,
including Cadence, are available at the Si2
Samta Bansal, senior product marketing manager for Encounter
Digital Implementation at Cadence, likes the idea of a dictionary. "The
community has to get together and talk the same language," she said. "For
example, in manufacturing, we talk about ‘via first,' ‘via last,' and ‘via
middle.' I don't think everybody in the community has a clear idea of what
these terms exactly mean and what their impact is. A dictionary can at least
serve as a first reference guide."
Manufacturing and Test
Meanwhile, the 3D-IC Alliance
is focusing more on the manufacturing side, and has released the Intimate
Memory Interconnect Standard (IMIS) to standardize vertical interconnect
requirements. The Alliance
maintains a literature page
with an updated listing of articles, blogs and publications on 3D ICs.
Another area calling out for standardization is 3D IC test. As
described in a whitepaper
from Asset Intertech, two
emerging standards - IEEE
1149.7 compact JTAG and IEEE
P1687 internal JTAG (iJTAG) - can be deployed together to embed test
structures in 3D ICs.
But first things first. We can't have a useful 3D IC
standards discussion if we don't agree on what a "3D IC" is.