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Analog and RF IP creation isn't easy in this era of rising
complexity and shrinking process nodes. Supporting the integration of IP into
SoCs poses many difficulties as well. Jacob Rael, senior manager at Broadcom, is an analog/RF designer who
knows these challenges well.
In the short video interview below, Rael describes his work
in the radio group at Broadcom, discusses challenges with analog and RF IP creation,
describes a verification process that starts with behavioral digital models,
and explains how his group makes things easier for SoC integrators.
If video fails to open, click here
This interview was conducted at the June Design Automation
Conference, following Rael's appearance on a lunch panel about Silicon
Realization that I
blogged about previously. At the panel, Rael talked about the difficulties
of scaling analog and RF to new process nodes, and noted that 65 nm is the best
process to support analog and RF. He also talked about Broadcom's use of simple
behavioral digital models to verify connections and functionality.
Given that the EDA360
vision paper emphasizes the need for greater support for IP integration, I
asked Rael whether there's a need for more tools to help ease the process of
analog and RF integration into SoCs. "I think that would help a lot," he
replied. "For example, the flow we use right now for timing model development
is kind of haphazard. We use an LVS tool from one vendor, then we use [Cadence]
Assura to get the parasitic variation, and then we use a different tool to do
the back annotation. A really simple task like getting a capacitor back-annotated
to a node can spiral into weeks of work."
With more and more analog and RF blocks going into SoCs of
all types, better support for analog/RF IP creation and integration will clearly
become a critical feature of tomorrow's EDA environments.