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Cadence last week announced the publication of two books -
one about the Universal Verification Methodology (UVM), and one about
transaction-level modeling (TLM) design and verification. I noticed that there's
a lot of discussion about UVM in the TLM
book, and several sections about TLM in the UVM book. The current UVM 1.0 EA
(early adopter) release focuses on RTL and SystemVerilog. So, what's the
connection between UVM and TLM?
To gain some insights, I talked to Cadence co-authors of
both books. These include Mike Stellfox, co-author of TLM-Driven Design and
Verification Methodology, and Sharon Rosenberg, co-author of A Practical Guide to Adopting
the Universal Verification Methodology (UVM). Both noted that UVM provides
an infrastructure that will help facilitate the move to TLM design and
verification. They also talked about work Cadence is doing to extend UVM to TLM
verification and to multi-language support.
With the move to TLM-based design, "the verification problem
statement is the same. We still have to exhaustively verify a DUT [design under
test]," Mike said. "The difference is that the design is now captured at TLM,
not RTL. So, we wanted to leverage the best practices and proven methods that
were put into UVM, and extend UVM to enable it to work for TLM based designs."
TLM Already There
Reminder: UVM 1.0 EA is basically OVM 2.1.1 with the "O"
changed to "U," plus some minor enhancements. So, what is said here about UVM 1.0 EA also
generally applies to OVM 2.1.1. Tom Alsop, Accellera VIP technical steering
committee co-chair, issued a statement on uvmworld.org that Accellera
intends for UVM 1.0 EA to be backwards compatible with the upcoming UVM 1.0
release. Meanwhile, UVM 1.0 EA is an
"emerging" standard, not a full Accellera standard yet.
UVM 1.0 EA uses OSCI TLM 1.0 APIs to communicate among
verification components (called UVCs in UVM). Communicating at the transaction
level facilitates reuse, and opens the door to communication with UVCs written
in different languages. Sharon
noted that all of TLM 1.0, including analysis ports, are included in the OSCI
TLM 2.0 release.
Transaction-level modeling is nothing new for OVM/UVM users.
As the UVM book notes in chapter 4.6, "TLM has been used within testbenches for
many years. In general, any testbench is at the transaction level if it has
components that create stimulus or that do coverage or checks using
transactions rather than using clock cycle level behavior. To verify RTL DUTs,
such testbenches use transactors (sometimes called bus functional models or
BFMs) to convert between the transaction level and the RTL."
So, conceptually, the move to a TLM design and verification
flow is not a huge leap for verification engineers. In this sense they're ahead
of their designer colleagues. What's new is the verification of TLM design
Adding TLM Support
An important principle that comes with TLM design and
verification is "localization." As TLM book co-author Yoshi Watanabe noted in a
author roundtable discussion, if you make design decisions at the transaction
level, you want to verify those decisions there - not wait for RTL
While it's not part of the emerging standard yet, Cadence
has done some work to extend UVM for TLM verification. Mike noted that UVM
today uses a signal-level driver to connect to RTL designs. "For TLM, we
basically replace that driver with a driver that drives at the transaction
level. It's pretty natural because the rest of the testbench is usually at the
transaction level anyway."
noted that Cadence UVM extensions include the "generic payload" (GP) concept
from the TLM 2.0 standard. Basically, this makes it possible to work at a high
level of abstraction without specifying a protocol. There's further discussion about
the UVM GP package and other UVM TLM extensions in the TLM book.
Finally, as was done for OVM, Cadence is working to bring
multi-language support to UVM. This is key for verifying SystemC TLM
designs. Multi-language support will also include the Specman e
language. The TLM book states that "e is the best language for TLM
verification" given its maturity, independence from design language,
abstraction, high performance, and aspect-oriented programming abilities.
Cadence has also adopted UVM SystemVerilog for TLM
verification, even though SystemVerilog was really designed as one language for
design and verification based on RTL Verilog.
As of today, Mike noted, many users of high-level synthesis still
do most or all of their verification at the register-transfer level. "We're not
really helping the customer if we can't move verification up to the same [TLM]
level," he said. "The fact that we're doing it by providing this methodology in
the [TLM] book, and doing it based on something already familiar to the
verification community [UVM], will accelerate the adoption of TLM-based
The only downside here is that forward-looking OVM/UVM users
might need to buy two books! Ordering information is available by following
the links in the second paragraph of this posting.
Other Blogs About the
UVM Book is for You and U but not Ewe (Cadence Functional Verification)
Interview: UVM Book Authors Sharon Rosenberg and Kathleen Meade (Cadence
Book: TLM-Driven Design and Verification Methodology (Brian Bailey,
Roundtable: New TLM Design and Verification Book (Cadence Industry