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There aren't any real "show stoppers" in terms of process or design technology for 3D ICs with through-silicon vias (TSVs), according to a Sept. 3 webinar featuring speakers from GLOBALFOUNDRIES and Cadence. But reduced manufacturing costs will be needed for widespread adoption.
The webinar was part of a Digital Implementation and Signoff Webinar series that ran in late August and early September. I already wrote about two previous webinars, including one on on-chip variation (OCV) and one on silicon-on-insulator (SOI) design flows.
Why 3D ICs? John Iacoponi, senior manager of GLOBALFOUNDRIES Technology Research Group, had some interesting perspectives. He cited interconnect speed and bandwidth demands approaching the 100 Gbits/second range, miniaturization, the high costs of moving to new process nodes, and the requirement for IP reuse. A major driving force in the future will be growing memory bandwidth requirements.
3D IC Process Technology
An important point about 3D ICs is that one size does not fit all. John said that the marketplace will support high-performance products with large die and packages, mobile products with multiple die, and low-cost, small-form-factor products with fine pitches and thin packages. Many 3D ICs today use silicon interposer layers, but in the future, pure vertical stacking will offer higher integration. Integration schemes include "via first," "via last," and "via middle."
John reviewed process challenges including temperature requirements, barriers, metal fill, TSV plating, wafer thinning, and bonding. None are "show stoppers," although bonding technology is not yet mature. But innovation, higher throughput, and cost reductions are needed in many of these areas, he noted.
3D IC Design Challenges
A "revolution" in design tools is not needed for 3D ICs, said Samta Bansal, senior product marketing manager at Cadence. "There are new considerations for chip designers, but really, I don't think you need 3D tools for all this," she said. Rather, she said, existing tools can be expanded with an understanding of new constraints and a third dimension.
What capabilities are needed? Samta cited three areas:
IC/package co-design will be critical for 3D ICs. This will allow users to plan and visualize environments across multiple fabrics, and will support thermal and mechanical analysis across the system. 3D design for test (DFT) is another critical area, Samta said, because of the need to test the entire system and diagnose potential problems. Several standards are under development in this space.
Samta went on to show how Cadence has added a modeling and database infrastructure to support 3D ICs in its Encounter Digital Implementation System, including thermal analysis and 3D floorplanning. Cadence has had IC/package co-design for several years, and nothing drastically changes for 3D ICs, she said. Samta noted that Cadence is working with customers on various stacking styles, including memory over logic, logic over analog, three-die stacks, and configurations both with and without silicon interposers.
What's critical, she said, is to manage costs so that 3D ICs can be deployed in cost-sensitive applications. This can only be done through a strong ecosystem. "In the end, unless we can manage the cost aspect, it [3D IC] is not going to become mainstream," Samta said. "So we have to work very closely with foundries, systems houses, designers, and OSATs [assembly and test]."
This and other webinars in the series will be archived approximately one week after presentation.
Recent Cadence Community blogs on 3D ICs:
Samta Bansal: My DATE With 3DIC Technology
Rahul Deokar: EDP Symposium Discovers an Inconvenient Truth with a Shot of 3D
Richard Goering: EDA Workshop: A Reality Check on 3D ICs
Rahul Deokar: DAC 2010 - A "Coming Out" Party for 3D-IC Design