Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Titled "Power Management in a Mixed-Signal RF Environment," the panel was moderated by John Donovan (right), editor/publisher of Low-Power Design. The introduction says it well: "Digital engineers have long had a hard time understanding what their analog colleagues were doing - and neither wants to get anywhere near RF. But with most new designs being mixed-signal and increasingly wireless, that's a luxury designers can no longer afford."
The panel was conducted in Q&A format. Below are snapshots of some of the more interesting questions and answers I heard.
Q: To what extent can you define a power budget at the algorithmic level, and expect to hit it when you tape out?
Pangrle - Make sure you're in the ballpark initially. Then develop TLM models, and improve the estimates as you refine them. When you get to the gate level, do a power analysis and pull it back up to run an overall check on your system.
Wang - There has been some early work in algorithmic power estimation, but most is still in research. "From what I can see, the big problem here is the modeling."
Ying - Energy efficiency is a "multi-tier system-level problem" encompassing the operating system, the software that manages different modes of operation, and the system-level control IP.
Q: How accurate are the black-box analog models you get from IP vendors? What needs improvement?
Wang - It's a two-phase problem. One is the actual modeling of analog/mixed-signal IP, and the other is creating a good model to assist with SoC integration. "The modeling part for integration is relatively easy and that should be tackled right now."
Davis - At Cypress we characterize block-by-block. But our programmable SoCs pose challenges. We never know how the IP will be used in the end system.
Ying - There's a need for non-dynamic circuit simulation for characterization, "maybe some sort of rules-based electrical check that allows you to propagate signals across the entire chip."
Wang - Designers traditionally use functional vectors to get activity information, but this is becoming outdated. Better to run real system-level applications using an accelerator/emulator or FPGA prototype.
Q: Is it reasonable to build all power and frequency management into an SoC, and if not would you have to design a custom external power management IC (PMIC)?
Wang - This depends on cost and application. An external PMIC may have cost advantages, but an application may require a tighter integration of power and timing. Commercial PMIC IP is available (National Semiconductor, Texas Instruments) and it comes with driver software and tools.
Pangrle - If you're designing an external PMIC you may be able to pick a technology that's more applicable for doing power management. Putting power management on chip may cause noise problems with RF circuits.
Q: If you integrate black-box IP from a variety of vendors, do you get enough information from the models to avoid a respin?
Wang - "The short answer is no. We must improve this situation." IP models must include timing, behavior, power, noise, and physical layout constraints.
Davis - All Cypress analog IP is designed in-house, and we have a very rigid process for characterizing it, as well as a reuse "vault" for SoC designers.
Donovan - "It has been suggested that SoC design is not so much about design as it is integrating IP from a variety of vendors, so the lack of uniformity in the IP models they're providing is a notable problem that needs to get resolved."
Pangrle - "If you're bringing in analog IP you need the expertise on the SoC team to understand it. You can't take a block of analog IP and just place it anywhere on chip."
Q: Can you realistically do parasitic extraction at the board level with any degree of accuracy?
Ying and Wang agreed that no one extraction tool will handle all requirements. Ying noted that even point tool vendors in this area have multiple solutions.
Q: Is there a unified set of tools or techniques that will ease analog/mixed-signal verification?
Ying and Pangrle both talked about mixed-simulation environments that work across multiple domains and multiple levels of abstraction.
Wang - "From the Cadence point of view, two areas need to be improved. One is the tools themselves, and the other is that we need new thinking and a new methodology for mixed-signal design and verification." For example, the metric-driven verification used in the digital world should be applied to analog/mixed-signal.
A Quick Conclusion
As suggested in that last quote from Qi Wang, it's time to apply the kind of attention we've given to digital low-power design to analog/mixed-signal and RF. Hats off to EE Times for including this topic in its Power Management conference.
Some Other Resources
Luke Lang of Cadence has written two blog postings on analog/mixed-signal low power design for Chip Design Magazine's low-power design community.
The Cadence Community launched a low-power blog this summer. An ongoing series of postings by Neyaz Khan discusses power management for digital mixed-signal systems.
John Donovan's Low-Power Design site has a number of insightful articles, and includes a blog written by Steve Leibson of Cadence.