Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
The Open Verification Methodology (OVM) has helped thousands of verification engineers build structured testbenches and run coverage in digital environments. Can the same advantages be leveraged to verify analog IP and mixed-signal SoCs? Yes, according to a paper planned for CDNLive! Silicon Valley Oct. 26.
Why apply OVM to the mixed-signal world, how, and what are the challenges? To get some background on the subject, I talked to two of the paper’s co-authors – Neyaz Khan, architect at Cadence, and Yaron Kashai, distinguished verification engineer at Cadence.
Analog Complexity Grows
Yaron noted that analog IP today is complex and reconfigurable, with digital control and requirements for power management. The result is a very large state space. Engineers thus need to measure their progress and create stimulus in a structured way, and OVM helps achieve both goals.
OVM provides base class support for hierarchical sequences, thus allowing complex stimulus generation. Yaron noted that engineers can use OVM to inject analog sequences. They can then drop in checkers that look for particular waveforms, shapes, or voltage levels. It’s also possible to drive digital and analog testing with one testbench and one verification plan. These capabilities “provide a lot of value compared to the way analog is usually designed, which is by eyeballing stuff,” he said.
Analog coverage “metrics” can be provided in a variety of ways, Neyaz noted. For instance, if you run a frequency sweep on a circuit, you can look at the gain. If you use voltage scaling, you can look at what voltage level you’re running at any given time.
Applying an OVM-based methodology to analog/mixed-signal verification raises some challenges. One is the cultural difference between digital verification engineers and analog designers. Yaron noted that analog designers interactively run simulation by hand, and rarely run regressions, whereas digital verification engineers are strongly focused on regression testing.
“When advanced [digital] verification techniques came around, people needed education and training,” Neyaz noted. “What makes the problem a little harder here is the need for some cross-domain knowledge. The verification guy may need to understand something about the analog, and the analog person may need to understand a little about the testbench.”
OVM, as you probably know, will be succeeded by the Accellera Universal Verification Methodology (UVM) standard. Thus far UVM is maintaining backward compatibility with the OVM 2.1.1 release, and everything said in the CDNLive! OVM paper should apply to UVM. For an update on UVM 1.0, see Tom Anderson’s recent blog.
Case Study – It Can Be Done!
The CDNLive! paper, scheduled for the SoC Realization track at 4:15 pm Oct. 26, will present a case study that applied OVM to analog/mixed-signal verification. The abstract, now available on-line, says:
This paper is based on pioneering work done through a partnership between LSI Shanghai and Cadence. A prototype was developed to demonstrate the benefits of applying an OVM-based verification flow to the verification of a complex analog block that is part of a live project. The advantages of this flow and positive results will be highlighted. The presenter will share his experiences in: 1) Applying the OVM to the verification of complex analog IP blocks and 2) Applying digital-centric mixed-signal verification (DMSV)-based techniques to model analog IP and use it in an OVM-based verification environment.
While CDNLive! registration is currently closed, a wait list is available, and technical sessions will be available on a microsite after the conference.