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A common belief is that "analog doesn't scale." But analog/mixed-signal design can indeed work at advanced process nodes. An inside look into how, and what the challenges are, comes from a recent partnership between GLOBALFOUNDRIES and Cadence that produced a 28nm analog/mixed-signal design flow development kit.
My take from this experience is that analog/mixed-signal at 28nm is challenging but not prohibitive. Yes, leakage and parasitics can be more problematic, and analog blocks won't shrink as much as digital blocks, but there are no big roadblocks that make analog/mixed-signal design at this node unfeasible. And now, thanks to the above-mentioned partnership, we have a reference flow that shows just how it can be done, using GLOBALFOUNDRIES "gate first" high-k metal gates (HKMG) 28nm technology.
Why put this flow together? "There are new effects at 28nm that people might not be aware of," said Bob Chizmadia, director of analog/mixed-signal technologies at Cadence. "When you put a reference flow together, it shows an example of how designs should be done."
What's In the Flow
One thing to clear up right away is that a foundry process reference flow is far more than just a "demo." As Bob said, "it's significantly more comprehensive. It would take a designer a week to go through all the documentation for the entire flow. They get the entire reference database, the PDK [process design kit], standard cell libraries - it's much more in depth than what you could get from a demo."
Specifically, the flow covers the following:
Cadence tools in the flow include Virtuoso Analog Design Environment (ADE), Virtuoso Layout Suite (VLS), and Virtuoso Schematic Editor (VSE). As Bob noted, however, "we actually drive everything through Encounter, so we show both sides of the mixed-signal implementation."
Challenges at 28nm
So, what was learned about analog/mixed-signal at this process node? For one, Bob said, "parasitic effects at 28nm are much more significant than at other nodes." The flow thus places a lot of emphasis on looking at parasitics early in the design, and providing techniques to sweep parameters to find out which are sensitive to parasitic effects.
A second issue is device leakage, and that makes it important to look at different threshold voltages. "There are challenges getting circuits to operate across all corners," Bob noted. "You do end up with a lot more corners and you have to be very judicious knowing what effects to look at for each corner."
Finally, there's a need to do earlier floorplanning and to be aware of what is going on in the physical design. "You can't just throw the design over the wall to layout. You need to account for what's going on in the layout earlier," Bob said.
To get some further perspectives, I talked to the team of Cadence engineers who developed the reference design. With its 28nm low-power process, they noted, GLOBALFOUNDRIES was able to maintain leakage characteristics similar to those seen in 40nm "general" processes. Thus, there was no need to redesign architectures used for 40nm non low-power processes.
I think the above information should be encouraging. Is 28nm analog/mixed signal design challenging? Absolutely. Is it so daunting that only a handful of leading-edge users will ever try it? It appears that won't be the case.
Thanks Richard. There is evidence that certain analog functions can be created with digital logic enabling scaling in tandem with the rest of the digital system. Stellamar is doing this with an ADC for some sensing applications, and they are working on the other analog functions as well. It is fairly interesting (www.stellamar.com).