Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Static statistical timing analysis (SSTA) can provide good timing accuracy by reporting statistical distributions instead of absolute numbers. But many design teams feel it's too early to deploy full SSTA. An alternative method available with the Encounter Digital Implementation System, called Design-Specific On-Chip Variation (DS-OCV), provides many of the advantages of SSTA in a simpler flow. At the recent CDNLive! Silicon Valley, Michio Komoda, senior engineer at Renesas, described his company's use of this methodology.
You can listen to the presentation and download the PDF from the CDNLive! On-Demand web site (see presentation titled Less Pessimism by Applying Design-Specific OCV Analysis in the Silicon Realization III session. Access requires a free Cadence.com account). The following Q&A interview with Komoda-san was conducted following the presentation.
Q: What are the problems with traditional static timing analysis (STA)?
A: There are two major problems. First, Spice model corners cannot be defined as variations, so some pessimism is introduced. Secondly, OCV is pessimistic. With OCV it is difficult to define a single value, because it is sensitive to circuit structure. The pessimistic value is the most applicable.
STA gives you the simple sum of every result, while there is no correlation between the corner and OCV in actuality.
Q: Does STA require a large number of corners?
A: If we define many corners, the STA run times are huge. Another strategy is that we use 3 or 4 selected corners and apply some guardbands. That also introduces pessimism into STA.
Q: How far off are the STA measurements, and what are the consequences?
A: It depends on the circuit, but it seems to be 10 to 20 percent. This is safe from the standpoint of yield, but if we need to speed up timing, it makes for a long design time. Getting the final 100 picoseconds may take more than one week. Also, even if we fix the timing, we may need to introduce low Vt cells that are high leakage.
Q: What are the advantages of SSTA?
A: Accurate timing! SSTA also provides a 10 to 20 percent acceleration from STA turnaround time. Design time is reduced, and the leakage is reduced by around 20 percent.
Q: What are the advantages of DS-OCV?
A: We can use a statistical result. OCV is still set to a single value, but it is based on SSTA results. It is a more aggressive approach than normal OCV using a worst-case corner.
Q: Do you run DS-OCV on all nets, or just a few critical nets?
A: Critical nets. With 1,000 nets maybe we run on 1 or 2 percent of all nets
Q: Why not use full SSTA?
A: We still have some concerns about SSTA. One concern is slower run time. Also, a statistical library is required for all cells, and this is not practical. The library size becomes huge, and this is not good for management. Another issue is how to fix timing violations. Today there is no way to do timing-driven layout based on SSTA.
In the future, we plan to adopt SSTA. But SSTA cannot be deployed immediately. We need to develop an SSTA design flow.
Q: How will full SSTA compare to DS-OCV?
A: Leakage reduction is the most important issue. With full SSTA we will get more leakage reduction.
Q: What needs to happen for full SSTA adoption?
A: We need automated timing-driven layout and fixing by SSTA. That is the key issue for SSTA signoff, especially for leakage reduction.
Related Blog Post
OCV Webinar: Statistical Timing Finds Its Niche