Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
As anyone who has been through the process knows, a complete (all layer) silicon respin is extremely time-consuming and costly. At the recent CDNLive! Silicon Valley, Ranjit LoboPrabhu, back-end lead implementation engineer at Netronome, discussed a better approach. In a paper co-authored with Bob Dwyer of Cadence, LoboPrabhu described a flow that can implement "mega ECOs" in just a few metal layers, with huge cost and time savings compared to full respins.
You can listen to the presentation and download the PDF from the CDNLive! On-Demand web site (see paper titled B0 in A1: Implementing Metal-Stepping Mega ECOs and the Associated Risks/Rewards in the Silicon Realization II session. Access requires a free Cadence.com account). After the presentation, I conducted the following Q&A interview with LoboPrabhu. For quick clarification, A1 refers to a metal-only revision, while B0 is a complete all-layer respin.
Q: What kinds of chips are you designing at Netronome?
A: Netronome is a fabless semiconductor company. We make silicon for our Network Flow Processors. Our previous process generation was 65nm in a 206mm2 die, about 60 million placeable gates. Going forward as we partner with other companies in the networking industry, we will be designing ever larger chips and integrating complex chips onto a single piece of silicon.
Q: How common are post-mask ECOs, and why do they occur?
A: They are very common in the industry. Many times you don't get everything right the first time. You need to get a product out there so that you have something to sample, but then you may have to fix something you overlooked during verification/signoff, or have to add features your customers want.
As a simple example, perhaps there is some kind of logical error, where you mean to "OR" two bits together but you "AND" them. Or you may need to add states to a state machine. By "mega" ECOs, we mean major changes that someone has requested.
Q: I understand that B0 is a complete respin, but what exactly is A1?
A: With A1, just the metal layers are re-taped out and re-made into masks. If you manage to limit the changes to selected layers, say metal layers 1 through 3, that's a significant cost savings. That's compared to 35-40 layers for a full respin.
Q: As you noted in your presentation, a post-mask ECO using the A1 approach cannot add or remove standard cells. So how do you make the logic changes requested in the ECO?
A: Typically you have some spare cells sprinkled around the design. You can use these cells to perform a particular logic function. What we did is create spare cells from redundant logic. If you re-optimize certain functions, you can gain some spare cells that can be retasked.
Q: You're still doing a new tapeout and making new masks with A1. What's the time and cost savings compared to a full respin?
A: It's about one-third to one-fourth the cost, depending on the number of layers you have to change. There's less time involved with the tools because they're changing fewer things. There is also less time in the fab. The product comes out 3 to 4 months sooner, making it easier to hit the right market window.
Q: Your presentation talked about using three Cadence tools for this flow - Encounter Conformal ECO, Encounter RTL Compiler Physical, and Encounter Digital Implementation (EDI) System. How are these employed?
A: Conformal ECO is the "mastermind" behind everything - it conducts the whole orchestra. Conformal ECO sees the changes between your implemented tapeout and your new netlist. It detects the changes and it creates a patch. Then it optimizes that patch by mapping it to spare gates. When you do logical equivalence checking to the netlist, you get the feedback of how big a change you are trying to implement in terms of mis-comparing logic.
Conformal ECO runs RTL Compiler Physical under the hood. We use RTL Compiler Physical to map new logic into spare gates. It's a really powerful engine. If something breaks, however, we can't debug it from Conformal ECO, so we need to bring up RTL Compiler Physical directly. We then use EDI to finish up the routing.
Q: Your presentation talked about a post-mask ECO you implemented in a PCI Express controller. Did you avoid a full respin, and what were the time savings?
A: Yes. If we'd done a full respin it would have taken 5 to 7 months. This [A1] took 3 months of effort, but that included putting the flow in place, which took 1 to 2 months. So if we'd had the flow in place, it would have been more like a month or two.
Q: Are there times when the A1 approach won't work, and a full respin is needed?
A: Yes. You need to go to a full respin if you're touching a large number of blocks, or you're pretty sure you can't use spare gates. Then it becomes a blank slate and you can add standard cells and do whatever you want.
Note: A recent blog by Bob Dwyer, CDNLive! Silicon Valley 2010: User Papers Explore Digital Implementation, also discusses the LoboPrabhu presentation.