Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Process design kit (PDK) developers have been using the SKILL language to code PCells (parameterized cells) for over two decades. SKILL is a flexible, extensible, Lisp-based language that can do just about anything a programmer wants to do. But is there an easier way to create PCells? Yes, according to a presentation at the recent CDNLive! Silicon Valley.
The presentation was given by Romain Feuillette, PCell Team Leader at STMicroelectronics in Crolles, France. He discussed his experience benchmarking the PDK Automation System (PAS) tool and its Graphical Technical Editor (GTE). You can listen to the presentation and download the PDF from the CDNLive! On-Demand web site (see paper titled PCell Generation with the Cadence PAS Tool in the Silicon Realization IV session. Access requires a free Cadence.com account).
I attended the presentation and also spoke with Romain Feuillette separately. The packed room at CDNLive! showed keen interest. This is not surprising, given that PDKs are a foundation technology for all IC design. Easier PDK generation will provide better access to advanced process nodes, and make it easier to improve mature process nodes.
PCell Generation Challenges
In his presentation, Romain Feuillette noted that his group supports 20 different technologies with PDKs, ranging from advanced nodes down to 20nm as well as mature process nodes. There are a number of challenges. One that he spoke about is filling an octagonal ring with vias, a potential "nightmare" that can take a great deal of time. ST has a proprietary algorithm for this, but must then ensure that all possible PCell configurations are DRC clean. "We can spend 90 percent of our time fixing less than one percent of the problems," he said.
Romain Feuillette also spoke of a "disconnect" between the process developers and the PCell developers in Crolles. Today, he noted, the PCell developers manually import data from Excel files provided by process developers. In our separate conversation he explained further. "We get Excel files from the process people, and most of the time we don't have a routine or script to import them, so in most cases a [PCell] developer will just look at the file and write in the PCell. This is a manual process and can cause errors. We are in the process of implementing an improved way to import an electronic format design rule manual [e-DRM], most likely in XML format, straight into the PCell development tree structure to reduce the manual step."
Romain Feuillette's presentation briefly described PAS. The first step is to manually create a GTE file or "book," a document that includes text and graphics. This is the input to PAS, which automatically creates SKILL code for PCells. The main concern is that this manual process of creating a GTE file must be enhanced with an ability to digest an XML e-DRM.
Faster PCell Generation
Pointing to the octagonal ring example, Romain Feuillette noted that a few GTE frames can represent hundreds of lines of SKILL code. For example, filling vias in a 45 degree rectangle used 4 GTE frames instead of 300 SKILL code lines.
"GTE doesn't require a lot of coding," Romain Feuillette said in our separate conversation. "We can have a newcomer use this tool. It's really easy to use compared to coding in SKILL, which requires some experience." Another advantage of PAS, he noted, is that it can automatically import data from Excel CSV files.
But there's still some work to be done. Right now, he said, the display time for GTE frames takes too long. There are also issues related to display.drf file modifications, GTE frame size limitations, and the time it takes to fill polygons with vias. Romain Feuillette noted that Cadence support is working on these issues.
It was interesting to hear from a user who is still in the process of benchmarking a new tool and is considering its advantages and limitations. In this case, it's a tool that could someday have a broad impact on process development.