Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
As the EDA360 vision paper notes, tool and methodology support is needed for IP integration into systems-on-chip (SoCs). A standards-based ecosystem needs to be part of this approach. One standard that can play an important role is IP-XACT, which provides a metadata documentation format for packaging, integrating, and reusing silicon IP blocks from different sources.
A newly archived Cadence System Realization Alliance webinar explores the role of IP-XACT in transaction-level modeling (TLM). The webinar was presented by System Realization Alliance partner Magillem, a French company that offers products and services for IP-XACT deployment. Their products include Magillem Platform Assembly, a tool that guides the SoC designer through virtual platform assembly and IP configuration. As noted on the Magillem web site, this product is tightly integrated with the Cadence Incisive Enterprise Simulator.
IP-XACT was developed by the SPIRIT Consortium, which merged into the Accellera standards organization last year. Officially, IP-XACT is now the IEEE 1685 standard. It provides a human-readable format for interoperable IP module descriptions and tool interfaces. Deliverables include an IP metadata schema, bus definitions, component schema, syntax and schematic rules, configuration and generation interfaces, and standard interfaces to tools.
SystemC and IP-XACT "Convergence"
In the webinar, Suresh Jeyachandran of Magillem discussed the use of SystemC and IP-XACT in virtual platform environments. "We know that the convergence between SystemC and IP-XACT is natural, and will contribute to a strong and coherent solution," he said. He went on to note that current models and platforms rely mostly on proprietary languages and formats, including pure C++ and specialty flavors of SystemC. With multiple IP providers and multi-site design teams, this lack of standardization is becoming a bottleneck.
SystemC makes it possible to design models based on common definitions and coding rules, and comes with protocol libraries, compilers, and simulators. IP-XACT provides an "electronic data book" that supports connectivity, abstraction definitions, configuration, memory management, and assembly information. It allows the generation of a variety of files for verification, test generation, documentation, packaging, and software.
The Magillem Platform Assembly tool includes an IP editor, register editor, API support, version management, and IP-XACT generation from legacy models. It can also generate header files, register files, and a "TLM skeleton." Incisive provides TLM-aware verification and debugging along with testbench automation and support for the Universal Verification Methodology (UVM). Cadence also provides high-level synthesis with C-to-Silicon Compiler. The result, said Jeyachandran, is a "complete TLM flow."
Users evaluate IP-XACT
Separately, an informal user survey on IP-XACT was posted last year by David Murray of Duolog. It's an interesting look at how the standard is used, and what parts of it are most successful. It also looks at requested future enhancements. One such request is to become more of a system-level standard and address software. That's a challenge that a number of our "EDA" standards have - how to adapt to a changing design environment in which software is increasingly the main cost and the largest bottleneck.
The archived Magillem IP-XACT webinar is available here. It requires Cadence Community membership (quick and easy registration if you don't have it already).