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Early adopters are starting to design at 28nm and are running into some challenges, according to Rahul Deokar, product management director for digital Silicon Realization at Cadence. In this interview he talks about challenges designers are experiencing due to design rules, lithography, low power, mixed-signal design, and giga-gate/gigahertz complexity, and shows how a "unified" digital flow based on Silicon Realization (unified intent, abstraction, and convergence) can help. The interview follows a recent Cadence announcement of a unified digital flow.
A: From the manufacturing side, the biggest thing is the explosion in the number of design rules. Whenever you move to a new process node, the design rules just explode. Tools take more time to handle all these rules, and the relationships and overlaps and conflicts between them. There's an impact on turnaround time.
The other big manufacturing issue is lithography. At 40nm you could get away with doing lithography simulations. But at 28nm, given the size of the designs and the complexity of lithography problems, simulation doesn't work. You need more intelligent techniques that can make appropriate tradeoffs and handle lithography.
Apart from that, there are challenges in three areas: giga-gate/gigahertz design, low power/mixed signal, and advanced technology integration such as 3D-ICs.
Q: What are the challenges of giga-gate/gigahertz design?
A: One challenge is just being able to reach and exceed gigahertz frequency. There are a number of new cell phones coming out, and all of them have processor speeds of 1 GHz or more. These companies need help in meeting this performance, and they're looking to us.
On the giga-gate side, customers are moving to bigger designs earlier than anticipated, and they need to move to higher levels of abstraction. I don't mean system-level design or TLM; I mean abstraction at the gate level and physical netlist level. They are also looking to us to provide hierarchical solutions. They need to partition the design hierarchy and leverage multiple-CPU infrastructures so they can do a better job.
Q: Low power design has been a challenge for a long time. What's happening at advanced process nodes?
A: Low power design cannot be an afterthought any more. Power reduction and efficiency are hard requirements right from the beginning of a design. Also, customers are adopting really advanced low power techniques, adding another level of complexity to the overall design methodology. They're doing things like power shutoff, dynamic voltage and frequency scaling, and substrate biasing.
Q: Cadence has announced a "unified" digital flow. What does "unified" mean and how is this flow from what the EDA industry has provided before?
A: Traditional EDA point tools are becoming increasingly inadequate. They are operating in fragmented domains, and as a result designers are forced to divide their SoCs into smaller designs just because of tool limitations. There's a lack of correlation between logic synthesis, physical implementation, and signoff analysis and verification. This results in long iteration cycles and a significant explosion in overall run times.
The new flow provides unified digital design, implementation, and verification based on the tenets of Silicon Realization, which are intent, abstraction, and convergence. The flow streamlines and connects capabilities like synthesis, floorplanning, implementation, and signoff verification. It includes Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, QRC Extraction, Encounter Power System and Encounter DFM technologies. We have brought these components together with intent, abstraction, and convergence, and we have also introduced a number of new technology features and core architecture innovations.
We've gone beyond digital to work seamlessly with Virtuoso custom analog tools and the Allegro system-in-package [SiP] tools. The flow lets designers drive breakthroughs in mixed-signal design and 3D-IC design, effectively allowing designers to extend beyond Moore's Law and perform "more than Moore" design.
Q: What's an example of unified design intent in this flow?
A: One example is silicon-proven 28nm intent from all of the major foundries, from electrical to physical to DFM. Another is the expression of intent through the Common Power Format [CPF]. The new release provides a power intent architect that lets designers specify power constraints in a very intuitive, graphical manner. It also provides an easy way to validate the power intent.
Q: What's an example of abstraction?
A: We have a new abstraction technology called FlexModels. It allows entire blocks of logic to be modeled simply and accurately, and to be optimized across logical and physical domains. It enables an order-of-magnitude compression of the initial design netlist while still retaining area and timing accuracy. This is what enables giga-gate/gigahertz designs.
Another example of abstraction is hierarchical, low-power macromodeling. If you specify your power intent at the top level, the tool can automatically push it down into the block levels. If third-party IP has power intent specified in CPF, the tool can automatically pull up that power intent as it integrates the IP blocks and does the top-level design.
Q: What's an example of convergence?
A: We have an end-to-end, RTL to GDSII ECO [engineering change order] flow based on our Conformal product. It does physically-aware, pre-mask functional ECOs. It automates difficult to implement ECOs, providing much faster convergence from RTL to final signoff. Another example of convergence is an advanced analysis engine that provides fast, single-step signal-integrity timing analysis and closure during the design flow.
Q: We've been talking a lot about 28nm. What does the new flow have for designers who are not yet at 28nm?
A: All the benefits we've talked about - performance, capacity, ease of use - are magnified at 28nm, but the benefits trickle up to other process nodes as well. If you're doing 40nm design and you move to this new flow, you will see the benefits.
Most of our mixed-signal customers are at older process nodes, but the new flow has many features for them. One new capability is full mixed-signal static timing analysis. We have the ability to traverse through the digital portions of mixed-signal blocks and do timing analysis, and do optimizations on the fly.
Q: 3D-ICs could include silicon at several different process nodes. What does the new flow offer for 3D-IC designers?
A: We are announcing a complete 3D-IC design environment with fully integrated capabilities, based on the tenets of Silicon Realization. It extends beyond digital to include full custom and packaging so that designers can get the best performance, size, cost, and power.
We have defined a consistent, unified 3D-IC integration file that captures intent. It drives creation, implementation, and verification across the three domains - digital, full custom, packaging. We have also defined chip-level abstractions and package-level abstractions. You can do concurrent chip-package co-design and bring in these abstractions through the OpenAccess infrastructure. For convergence, we have extended our in-design signoff philosophy to 3D-ICs. We can run extraction, timing, power, and thermal analysis across multiple die.
Q: What's driving the interest in 3D-ICs?
A: Different industries have different interests. For mobile phones, compactness is a primary driver. For video applications on mobile devices, bandwidth is the driver. Video is pervasive on mobile devices, but the current single-die infrastructure just cannot handle it. The number of pins needed to transmit video at such high bandwidths is just intractable. This seems to be a killer app for 3D-IC.
Networking, computing, and graphics designers are also looking at 3D-ICs. The interest right now is among a targeted set of leading customers. It's not for everybody yet. The good news is that people don't need dramatically new tools. However, existing tools need to be enhanced to be 3D aware. That's what we've done with this release.
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