Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
High-tech mergers succeed when two companies blend their technologies and expertise to come up with a "best of both" solution. That's the idea behind today's (Feb. 28, 2011) Cadence Verification IP (VIP) catalog announcement , which combines VIP and technology that originated at both Cadence and Denali Software before Cadence's 2010 acquisition of Denali. Here's a brief look at what each brought to the party (and yes, speaking of parties, the famous Denali DAC party is still on!)
One of the key messages of the announcement is that all Cadence VIP now works in major third-party simulation environments. Previously, Cadence had a very broad range of VIP - with over 30 protocols - but it ran only in the Cadence Incisive simulator. Denali, in contrast, had a smaller VIP portfolio, but it could run in any simulator. Instead of locking everything to Incisive, Cadence decided to open everything up.
Denali provided more than just inspiration. "What we're doing is putting the Denali testbench interface across all our VIP," said Tom Hackett, Cadence product manager for verification IP. "Denali customers had a high level of satisfaction with that technology. So we're taking something we know people like and applying it across the product line to provide a common testbench interface."
The testbench interface supports multiple languages including SystemVerilog, e, and SystemC, and methodologies such as OVM and UVM. Tom said the interface strikes a good balance between IP visibility and ease of use, thus avoiding complexity and resulting in "reduced time to first test." With the same VIP testbench interface available for any simulator, he said, users will be able to avoid manual effort and improve verification quality across all projects.
Expanded VIP Portfolio
While Cadence had a very large VIP portfolio before the acquisition, Denali provided some strategic additions. Examples include PCIe Gen3, SuperSpeed USB, IBM PLB (Processor Local Bus) and SATA 6G. Other new additions to the VIP catalog, stemming from work that originated at Cadence, include AMBA4, 40G/100G Ethernet, MIPI M-PHY, MIPI DigiRF, and MIPI UniPro.
Memory models developed at Denali are part of the new VIP catalog announcement as well. If you look at how they're structured, Tom noted, memory models are really VIP components. Like bus-oriented VIP, they have a monitor that verifies protocols are correct, and an agent that responds to stimulus. Further, memory models from Denali use the same testbench interface that is now being applied to all Cadence VIP.
One difference is that bus protocol VIPs are generic verification components that must cover all the functionality a designer might implement, while a memory model can be specific to a given manufacturer and part number. Denali had memory models for around 15,000 components. I will not attempt to list them here. But I'll mention the new memory subsystem modeling and verification support for wide I/O SDRAM, DDR4 SDRAM, LRDIMM, GDDR5, Flash ONFI 3.0, Flash PPM, and Flash Toggle2NAND.
Debug , Acceleration, and Unified Coverage
Another Denali technology that's being added to all Cadence VIP products is a trace debug feature that allows remote debugging without the need to obtain a copy of the customer's design. This gets around the NDA issues that inevitably arise when third-party IP is part of a design. Customers can turn the trace on, capture a detailed log file, and ship it back to Cadence without having to send a copy of the design. Cadence engineers can then debug what's going on in the model.
Technology originated by Cadence allows accelerated VIP on Palladium verification platforms using the Accellera SCE-MI interface. In fact, Tom said, this technology has been around for several years. "What's new is that we're rolling out a new generation of accelerated VIP that's compatible with simulation VIP so you can merge coverage results," he noted. Thus, whether the verification engine is a simulator, accelerator, or formal verification tool, coverage data from these three engines can be combined. (Cadence already had VIP support for formal verification).
Most Cadence VIP is available for evaluation on Xuropa.com/cadence. As I noted in a previous blog post, potential users can evaluate the software without signing a license agreement.
An overview of the new VIP catalog, including a listing of protocols and new capabilities, is available on line. An article by Tom Hackett at ChipEstimate.com provides further perspectives on the Cadence-Denali acquisition and the Cadence VIP offering.