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Design for manufacturability (DFM) is a fairly mature discipline that you don't hear much about these days. But a recent keynote speech outlined two interesting new developments. One new twist complements traditional model-based and rules-based approaches with pattern matching, while another brings DFM further up "in design" so that problems can be avoided during IC layout and analysis.
These emerging ideas were discussed by Vinod Kariat, Cadence fellow, at the International Symposium for Quality of Electronic Design (ISQED) March 15. His keynote speech was part of a plenary session sponsored by Cadence and moderated by Chi-Foon Chan, president and COO of Synopsys (who is also chair of the ISQED 2011 Steering Committee).
Kariat started his talk by looking at what's really important - the end product. He described a marketplace in which "smart phones are the new PC, and everything is application driven. It's no longer driven by high-end CPUs, it's being driven by mobile devices." He then mentioned two key business challenges - time to market and profitability.
"Ramp to yield is a very critical aspect of how we look at these products," he said. "Without good manufacturability you don't get the devices you want, you're not profitable, and you don't have time to market." How does DFM help? "What we really need from DFM is to bridge that gap and bring designs to volume at a time when you want them."
Kariat identified three algorithmic approaches that can be applied to DFM. The first two are traditional, while the third (pattern-based) is an emerging trend.
An example of pattern matching from Kariat's presentation is shown below. The top left shows a pattern that is DRC clean and that passes litho simulation. The bottom left shows two of these patterns next to each other; it's still DRC clean but will result in a lithography failure. If you identify this pattern as a yield detractor, you can avoid it in the future.
As Kariat mentioned, GLOBALFOUNDRIES uses a pattern-matching approach called DRC+ that provides a library of yield detractor patterns to avoid. A previous blog post describes DRC+ in more detail.
"In Design" DFM
The second trend that Kariat discussed involves moving capabilities from the foundry to the design flow. In a traditional flow, he noted, DFM is a post-signoff step. That's okay if there are only a few hotspots to fix, but if there are many, you have to "go back to the drawing board and start again."
"We're bringing more DFM engines into our implementation tools, so you have a convergent design flow rather than a flow with many iterations," Kariat said. An example from the custom flow is the use of electrical constraints on transistors to avoid downstream problems with stress and variability. An example from the digital flow is the ability to look at timing based on an accurate CMP analysis.
DRC+ is another "in design" DFM example, and it applies to both custom and digital flows. The concept can be taken further with automated fixes for problematic layout patterns, using techniques like moving edges.
DFM is not a problem that has been "solved," Kariat concluded. "We have more work to do. It's moving more and more up into the design flow, and as new technology features evolve, new challenges will come."