Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
3D ICs with through-silicon vias (TSVs) are in development by a few large companies, but they're a long ways from widespread adoption. What will it take to move this technology into the IC design mainstream? Panelists at the IEEE Electronic Design Processes (EDP) workshop April 8 came up with some interesting conclusions.
Representatives of three EDA companies (including one startup) said that EDA tools, a well-defined infrastructure, and a "killer app" will help drive adoption. An engineering manager at Texas Instruments noted other requirements - a niche application with a clear business case, standards, and a "bounded solution" that doesn't push the envelope more than necessary.
The panel was titled "3D ICs: Real or imaginary and what would speed adoption?" Panelists (shown left to right below) included:
Reiter opened the panel by noting that semiconductor companies will eventually move to 3D ICs because of cost, but they won't necessarily be cheaper initially. Instead, demands for lower power, higher performance, and smaller form factors will drive the first generation of 3D ICs. Also, 70% of 2D systems-on-chip have to be redone. 3D ICs can lower that risk and provide shorter time-to-market, heterogeneous integration, and architectural flexibility, he said.
An Inside Look at TI's 3D IC Development
Hernandez provided a fascinating look at TI's ongoing 3D IC development work. He noted that he's at a "critical stage" right now, analyzing data from second-generation TSV silicon and working on a third-generation test chip. Why the interest? "We have a very clear business need, we're comfortable the technology is there, and now we have to make sure it's what customers want and are willing to pay for." He said TI believes there's a "sustainable niche" in high-margin cell phones, a market the company is aggressively targeting.
TI is currently working on a wide I/O memory architecture and is not pushing the envelope in frequency. "We're not going to do 2 or 4 GHz," Hernandez said. "We believe it's a bounded solution. We know what the worst case IR drop will be, we know the worst-case coupling." Wide I/O, which is generally aimed at 3D ICs, was chosen because conventional DDR doesn't give enough performance within acceptable power and thermal profiles.
For TI, an infrastructure with clear business models is essential. "I was surprised with the changes in the existing [business] models we work with," Hernandez said. "Business models are just antiquated all of a sudden. If you have issues in assembly, who is responsible? At what point is the testing from the memory vendor the issue, at what point is TI the issue?" One impact: "It's going to increase cycle times as to who gets paid when."
Standards are another issue, and the emerging JEDEC wide I/O standard is having a substantial impact at TI. When engineers attempted to define the number of "direct access pins" they would use, a number of different business groups were affected by that decision, Hernandez said. With the JEDEC standard, the I/O interface is generally in the middle of the die. "Now you're telling chip designers they'll have a whole bunch of TSVs in the middle of the die," he said.
Fortunately, Hernandez said, the 3D IC effort has support from upper management, and a number of "top notch" engineers from different teams are working on it. "Decisions have to be driven by business, by a sustainable market, and based on that you get to the right solution. In this case it's a full TSV solution," he said.
Need for Infrastructure and EDA
Hernandez wasn't the only panelist to cite the need for an infrastructure with well defined business models. Martin (E-System) noted that big companies are using 3D ICs, but smaller companies will say "I've got no infrastructure, it's too costly and risky, and I don't see a big enough payback to go down that path. So you've got to get an infrastructure in there."
Petranovic (Mentor) said that "an effective ecosystem with co-operation on standards will be important. We need a clear business model as to who is going to own what. I think 2.5D assembly will be by OSAT (outsourced assembly and test), while 3D will stay with foundries."
EDA vendors are part of the ecosystem, and as Deokar (Cadence) noted, one question right now is whether the existing 2D flow can be extended to 3D ICs in an "evolutionary" fashion, or whether a "total overhaul" of EDA tools is needed to get to 3D ICs. "My answer is the first one [evolutionary] at least for the first generation of 3D chips," he said.
(In a presentation before the panel, Deokar described the EDA tool support that's needed for 3D ICs. For a detailed look at this presentation, see this week's posting in Steve Leibson's EDA360 Insider blog).
Petranovic listed EDA "challenges" including physically-aware architectural exploration, floorplanning, place and route, power grid design, thermal management, and thermally-aware design. Still up in the air, he said, is the level of modeling and extraction accuracy that is needed. There's also a question about what to do about the massive amounts of data that can be generated by multi-corner, multi-die analyses.
From an EDA perspective, Martin noted, "you've got to do early planning and understand where you want to put the TSVs and how they interfere with each other. You can't just do it at the back end." Proximity effects are critical, he noted. (E-System provides 3D extraction for signal and power integrity and analysis).
Looking for the "Killer App"
What's really needed to drive adoption, Petranovic said, is a "killer application" with new functionality at high volume, or a more-cost effective approach to an existing solution. Deokar suggested that the "killer app" is wide I/O memory. He noted the recent Cadence introduction of the industry's first licensable wide I/O memory silicon IP.
There's another factor that will help drive 3D IC adoption - enthusiasm. Hernandez said there's a lot of "excitement" among "top notch" engineers at TI, and noted that "you'd be surprised how much you can push your people to engage in this. We're working across the divisions and sharing resources to a degree I haven't seen for quite a while. We're all banking on this."