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Cadence today (May 3) is introducting the System Development Suite, a set of four connected platforms that support hardware/software co-development from the architectural level through final prototyping. The story is not just that Cadence now has solutions for virtual prototyping and FPGA prototyping, although these are significant new products. The big story is the way in which the entire suite works together, providing a continuum of platforms with fast migration from one platform to the next.
Why is such a continuum important? Starting from a very high level, the electronics industry is undergoing a change in which differentiation comes from software "apps" more than silicon. OEMs expect their semiconductor providers to supply not just chips, but hardware/software platforms ready for applications deployment. The EDA360 vision paper, published by Cadence one year ago, describes these trends, and defines the creation of application-ready systems as System Realization.
Application-ready systems must provide most of the software stack in addition to chips, packages, and boards. They thus require hardware/software co-development, and because time-to-market is pressing, this must begin well before silicon is ready. No one development platform will work for the entire flow. In most system design flows, four types of pre-silicon development platforms are needed - virtual prototyping, testbench simulation, acceleration/emulation, and FPGA-based prototyping.
Commercial offerings for virtual prototyping (or virtual platforms), simulation, acceleration/emulation, and FPGA-based prototyping are all available today, but there's a catch. Until today, no one vendor provided them all. Each type of platform is an island unto itself with little or no connection to the other platforms. Models and many other components of the environment typically cannot be shared between platforms and must be reworked at each step, and migration between platforms consumes a great deal of time. For these reasons, some design teams report that system integration and bring-up is the major time-to-market challenge they face.
The Cadence System Development Suite is based on three tenets. It supports standard formats and languages and third-party tools, and is therefore open. It provides rapid migration between platforms, and is thus connected. It scales up to meet capacity demands and high-volume software distribution requirements, and is thus scalable.
So what's in the suite? The key components are as follows.
The chart below shows how these platforms are used. While the Virtual System Platform is primarily aimed at pre-RTL software development, it can also be used in a post-RTL mode as an alternative to reference boards.
As I noted, the best part of the story is the way in which these platforms work together. For example, the Virtual System Platform uses the Incisive SystemC simulation kernel along with an extended version of the Incisive SimVision debug interface, providing a mixed TLM/RTL simulation environment. The same models and verification IP (VIP) can run in Virtual System Platform and Incisive. Incisive and the Verification Computing Platform, meanwhile, share compile, debug and run-time environments, and can run common accelerated VIP.
The Verification Computing Platform's SpeedBridge adapters, which allow connections to real-world hardware for in-circuit emulation, can also be used with the Rapid Prototyping Platform. The FPGA compile engine within the Rapid Prototyping Platform uses the same inputs as the Verification Computing Platform (as well as legacy Palladium products) and uses the same synthesis engine. Before FPGA place and route, the database can be taken back to Palladium for FPGA model verification.
Here's the really interesting part of the connection noted above. The big problem with FPGA-based prototyping is that bring-up times may take months. That's because FPGA-based prototypes typically require a separate design flow with FPGA experts, highly modified RTL code, and many, many iterations to ensure that the FPGA prototype matches the ASIC or SoC design. With its close link to Palladium, the Rapid Prototyping Platform works within the ASIC flow, requires few or no modifications to the ASIC RTL code, and can get a quick check of functionality before going through many hours of place and route. The result: bring-up times shrink from months to a few weeks.
A Deeper Dive
Of course, it doesn't help to have great connectivity without having great platforms to connect, and there's lots to say about each of the four platforms listed above. Further information about the System Development Suite, and a discussion about the "disconnect" of previous approaches, is available in a newly published whitepaper located here.