Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
If you're planning a 40nm or 28nm design with TSMC, you have two options for meeting design for manufacturability (DFM) requirements -- either buy EDA tools and run DFM checks, or turn to a services provider to run them for you. On May 9, Cadence became the first EDA partner to be certified by TSMC for DFM services, including lithography process checks (LPC) and chemical mechanical polishing (CMP) checks. Here's some background on how that happened and what that means.
As I wrote in an Industry Insights blog post at the time, in 2009 TSMC mandated model-based DFM checks for LPC and CMP at 45/40nm. While TSMC had mandated rules-based checks at previous process nodes, this was their first mandate for model-based DFM, which relies on modeling and simulation rather than conformance to design rules. A TSMC executive said at the time that "rules are getting so complex that there is no way the customer can use a complete rule-based solution."
TSMC provided two options for meeting the model-based DFM mandates. First, customers could use commercial tools such as the Cadence Litho Physical Analyzer and Cadence CMP Predictor. Secondly, they could use TSMC's on-line DFM service. At the time TSMC expected that the services option would primarily appeal to smaller companies who didn't want to make a big investment in tools.
New Process Node, New Approaches
Fast forward to 2011, where design teams are targeting both 40nm and 28nm. CMP simulation is now recommended at 40nm and mandatory at 28nm, while LPC remains mandatory for both. Meanwhile, model-based DFM consumes far more resources at 28nm. For example, it takes significantly longer to run LPC checks at 28nm than it does at 40nm. Given the compute resource requirements, even some larger companies who have their own tools are now interested in DFM services for full chip signoff.
TSMC decided to rely on its partners to provide DFM services, and Cadence was more than ready. "We ramped up very fast," said Manoj Chacko, product marketing director at Cadence. He noted that Cadence has a large compute infrastructure in its secure VCAD (Virtual Integrated CAD) chambers, which basically provide a private cloud computing resource that is scalable to a large number of CPUs. Cadence also has DFM expertise available on a worldwide basis, and has tools such as the TSMC-qualified Litho Physical Analyzer and Cadence CMP Predictor.
In brief, Cadence provides two DFM services - model-based lithography process checks, and CMP hotspot analysis. The goal is to help design teams fix lithography or CMP "hot spots" (yield detractors) prior to tapeout. "If we can identify systematic problems in the layout, that is where DFM checks come in," Manoj said. "We want to run [checks] early on and fix them in the implementation flow."
Turnaround Time and Data Security
How do the DFM services work? The customer ships Cadence DFM Services a GDSII or OASIS file, and Cadence personnel run the DFM checks using the secure infrastructure. TSMC jointly reviews and validates the report. Then the report is provided to the customer, along with layout fixing guidelines. Manoj said the turnaround time will typically be about two days for small designs and varies depending on the size of the design. After the chip has been checked initially, Cadence DFM Services re-checks the design using smart hierarchical technology, and these incremental checks can run in a few hours.
Customers don't have to use Cadence layout tools to use the DFM services, but those who have Virtuoso 6.1.5 can take advantage of the automatic fixing capability available with that product release. Automatic fixing is also available with the Encounter Digital Implementation System.
Of course, data security is a big concern whenever data is shipped outside a company firewall. Cadence provides a kit that allows customers to encrypt their data, which is decrypted after it arrives at the Cadence VCAD chamber. Only a select number of people from Cadence and TSMC have physical access to the secure environment. CPUs used for DFM services are scalable based on need and are dedicated to DFM.
Into the Cloud?
The TSMC-certified Cadence DFM Services represents a careful step into a cloud computing environment, albeit a private cloud at present. As DFM compute resource needs become even more intense at 20nm and below, DFM services in public or private clouds may become a good alternative, or a complement, to using tools in one's own environment.
Further information is available at the new DFM Services site or by contacting email@example.com.