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Semiconductor intellectual property (IP) reuse makes system-on-chip (SoC) design possible, but complex SoCs pose some really tough IP integration challenges. Panelists at the May 12 EE Times System on Chip "Virtual Event" answered five questions posed by moderator Mike Demler, technical editor at EDN, and helped identify some possible solutions to the challenges.
The one-day virtual conference, sponsored by Cadence, also Included a panel on high-level synthesis, a panel on hardware/software co-design, a webcast on the emerging DDR4 standard (see blog by Steve Leibson), and a keynote speech by veteran EDA investor Jim Hogan on SoC Realization (see blog by Steve Leibson).
Entitled "Building an SoC flow optimized for IP integration," the opening panel of the event included:
Here's a brief overview of the questions that were asked, and the answers.
1. What is the one biggest issue that impacts IP integration in SoC design?
Gianfagna: IP quality and consistency, and the associated design risks. "The dynamic range in this market is everything from ARM to two-man shops, and the integration risk and the completeness of the IP you get is all over the map."
Hand: "Having a way to measure the quality and consistency of IP blocks is probably the biggest single challenge we see in working with customers today."
Pakosh: Given the extreme complexity, it's time to revisit the basic architectural philosophy used today in SoCs. "Architecture is our biggest issue."
Sikand: The biggest issue is verifying the IP. The second issue is managing IP updates and bug fixes.
2. What standards are needed to support SoC/IP integration? Are you using IP-XACT? Are your customers using it?
Pakosh: There's a need to develop a standard methodology for controlling system-level functions. "It is done ad hoc today and is different from chip to chip."
Hand: Cadence supports IP-XACT in its chip planning and IP management tools. But IP-XACT as it exists today is not enough by itself. The industry still needs to define a set of standard deliverables. Customers don't yet see enough value in IP-XACT. "We need to get everyone together and have a willingness to move this forward."
Gianfagna: Atrenta Spyglass and GenSys products use IP-XACT. However, the latest IEEE 1685 IP-XACT standard "is still not completely supported and implemented. There is no reference implementation yet." Customers want the latest IP-XACT version, but by the time it's implemented, it may be obsolete.
Sikand: IP-XACT offers standardization around data management and IP, but has no support for dealing with derivatives.
3. As semiconductor IP evolves from blocks to subsystems, what challenges will arise?
Gianfagna: Subsystem blocks are "large massive entities" that include software and firmware. "You're dealing with more data, which puts more stress on the system and the robustness of tools. And it brings the hardware/software problem right into the IP reuse realm."
Pakosh: There are challenges in system management functions such as reset sequencing, error recovery, and security management. Providers need to test and guarantee operation across possible state changes and timings.
Hand: The move to subsystems needs to happen to deal with complexity. We need to manage the move correctly with well-defined boundaries, enabling encapsulation and isolation and making it easier to deal with very complex systems. Subsystems can manage themselves through integrated firmware.
4. How can SoC teams address the need for hardware/software co-design?
Hand: A key part is having models that allow software development. What is needed is a continuum from a virtual prototype model to simulation, emulation and rapid prototyping, as provided in the Cadence System Development Suite that was introduced last week. In this way, the models used by software developers are directly tied to implementation.
Gianfagna: "I think Cadence did an excellent job of articulating the way the market will evolve with the EDA360 vision paper published last year." The interesting part of that for Atrenta is SoC Realization, because "that's where the hardware/software interchange starts. It's not just hardware guys throwing a software model over the fence so software guys can start working on code early. The hardware team can change the hardware design to make the software more optimized."
5. How can designers ease the integration of analog/mixed-signal IP into their designs?
Gianfagna: There are two levels of problems, one inside the blocks and one at the interface level, where analog and digital blocks are hooked up. "I think the interface part is becoming more critical more quickly. It's becoming a chip killer."
Hand: The single biggest thing designers can do is "very carefully chose IP providers. Mixed-signal IP is very different from digital IP in terms of the expertise level required." All of the PHY IP that Cadence offers has significant mixed-signal content.
Pakosh: "Choosing your vendor partner is a critical piece. If he's only familiar with the A/MS PHY but has no integration knowledge of the controller, the onus is on the customer to do all that integration work, which is a huge task."
Sikand: "Best practices are a little different on the A/MS side of things. You really need a good way to deal with the flow of change. It's constantly evolving, it's not static." Design teams need a good way of tracking and updating changes across all functions of the IP, because there are a lot of constraints to manage.
From this discussion, what's needed for complex SoC integration seems pretty clear. The wish list includes:
The EDA industry has long ignored the challenges faced by IP integrators. Today Cadence and other companies -- including those who participated in this panel discussion -- are working on this "wish list" and are making SoC Realization a reality.