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Just in time for the Design Automation Conference (DAC), two new publications are providing fresh perspectives about 3D-IC design. First, the Global Semiconductor Alliance (GSA) has released a "3D-IC Design Tools and Services Tour Guide" for next week's DAC. Secondly, a new Cadence technical paper details a Silicon Realization approach to 3D-IC design.
The GSA guide was put together under the direction of Herb Reiter, who heads up the 3D-IC Working Group at the GSA. The 62-page guide is a compilation of inputs from EDA, R&D, market research, and services companies that have committed significant resources to 3D-IC technology. It's in its second edition, which allows some hindsight. As the guide points out, interest in 3D-IC technology has grown considerably since the previous edition, with questions shifting from "Why" to "How" and "When."
The introduction has a nice pro-and-con comparison of 2D, 2.5D, and 3D packaging choices. It discusses the benefits of 2.5D and 3D technology, such as heterogeneous integration, IP reuse, and small form factors. It also discusses the business and engineering challenges, noting that 2.5D silicon interposer configurations are "evolutionary" while 3D-ICs with through-silicon vias (TSVs) are "revolutionary."
The guide then hosts short sections provided by three market research firms, 14 EDA vendors (including Cadence), four R&D centers, and one value-chain provider (Open-Silicon). Since the guide was prepared for DAC, booth numbers are included. You can download a copy of the guide here.
Bringing Silicon Realization to 3D-ICs
As I blogged at the time, Cadence introduced a comprehensive 3D-IC design methodology in January 2011 that includes IC/package co-design, digital implementation, extraction, test, and custom/analog design. This methodology is based on Silicon Realization, which calls for design flows based on unified design intent, the appropriate use of abstraction, and convergence into a successful signoff.
The newly published paper, titled "Silicon Realization Empowers 3D-ICs with TSVs," goes into the Cadence 3D-IC flow in further detail. It shows, for example, how a graphical stacked-die editor captures the design intent of a 3D stack, which is then passed to floorplanning and implementation tools. 3D-aware floorplanning works with an abstracted view of the layout features on adjacent die, so designers can see what's on the die above and below. Convergence is provided by 3D-aware analysis and optimization tools for timing, signal integrity, and thermal effects, as well as IC/package co-design.
What I find most interesting about the methodology is how it cuts across traditional design "domains" such as custom/analog, digital, packaging, and test. In fact, IC/package co-design can be a starting point for the methodology. The traditional, compartmentalized, throw-it-over-the-wall approach to chip design will not work for 3D-ICs. Nor will a point tool approach - a comprehensive, end-to-end methodology is needed. This paper shows why.
You can download the technical paper here. A quick registration is required.