Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Just in time for the Design Automation Conference (DAC), two new publications are providing fresh perspectives about 3D-IC design. First, the Global Semiconductor Alliance (GSA) has released a "3D-IC Design Tools and Services Tour Guide" for next week's DAC. Secondly, a new Cadence technical paper details a Silicon Realization approach to 3D-IC design.
The GSA guide was put together under the direction of Herb Reiter, who heads up the 3D-IC Working Group at the GSA. The 62-page guide is a compilation of inputs from EDA, R&D, market research, and services companies that have committed significant resources to 3D-IC technology. It's in its second edition, which allows some hindsight. As the guide points out, interest in 3D-IC technology has grown considerably since the previous edition, with questions shifting from "Why" to "How" and "When."
The introduction has a nice pro-and-con comparison of 2D, 2.5D, and 3D packaging choices. It discusses the benefits of 2.5D and 3D technology, such as heterogeneous integration, IP reuse, and small form factors. It also discusses the business and engineering challenges, noting that 2.5D silicon interposer configurations are "evolutionary" while 3D-ICs with through-silicon vias (TSVs) are "revolutionary."
The guide then hosts short sections provided by three market research firms, 14 EDA vendors (including Cadence), four R&D centers, and one value-chain provider (Open-Silicon). Since the guide was prepared for DAC, booth numbers are included. You can download a copy of the guide here.
Bringing Silicon Realization to 3D-ICs
As I blogged at the time, Cadence introduced a comprehensive 3D-IC design methodology in January 2011 that includes IC/package co-design, digital implementation, extraction, test, and custom/analog design. This methodology is based on Silicon Realization, which calls for design flows based on unified design intent, the appropriate use of abstraction, and convergence into a successful signoff.
The newly published paper, titled "Silicon Realization Empowers 3D-ICs with TSVs," goes into the Cadence 3D-IC flow in further detail. It shows, for example, how a graphical stacked-die editor captures the design intent of a 3D stack, which is then passed to floorplanning and implementation tools. 3D-aware floorplanning works with an abstracted view of the layout features on adjacent die, so designers can see what's on the die above and below. Convergence is provided by 3D-aware analysis and optimization tools for timing, signal integrity, and thermal effects, as well as IC/package co-design.
What I find most interesting about the methodology is how it cuts across traditional design "domains" such as custom/analog, digital, packaging, and test. In fact, IC/package co-design can be a starting point for the methodology. The traditional, compartmentalized, throw-it-over-the-wall approach to chip design will not work for 3D-ICs. Nor will a point tool approach - a comprehensive, end-to-end methodology is needed. This paper shows why.
You can download the technical paper here. A quick registration is required.