Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Get email delivery of the Cadence blog featured here
Just one month after the announcement of the Cadence System Development Suite, three of the four hardware/software development platforms in that suite have become part of the TSMC Reference Flow 12. This includes the new Virtual System Platform, a virtual prototyping solution that provides early software development, as well as the Incisive Verification Platform and the Palladium XP Verification Computing Platform. The Reference Flow demonstrates an approach that is open (based on System C and other standards), provides connected platforms, and is scalable to the size and complexity of today's multi-core SoCs.
This is the second time that Cadence has collaborated with TSMC on an electronic system level (ESL) reference flow. As I blogged last year, TSMC Reference Flow 11 also had an ESL flow. This was a powerful endorsement of ESL methodologies from the world's largest foundry. Cadence worked with TSMC on high-level synthesis and on a "refine and reuse" verification methodology that allowed the reuse of models and testbenches at different levels of abstraction.
TSMC Reference Flow 12 involves more than just ESL, and Cadence also contributed technologies for 3D-IC test, in-design design for manufacturability (DFM), and analog/mixed-signal design. This blog post, however, will focus on the ESL portion of Reference Flow 12.
From Block Level to System Level
What's the difference between TSMC Reference Flow 11 and Reference Flow 12? "Reference Flow 11 was all block level," said Ashok Mehta, senior manager at TSMC. "Reference Flow 12 goes from the block level up to a virtual platform level, meaning that we show how to build a virtual platform. We estimate power on this core virtual platform and build a simple multi-media application using the virtual platform." In addition to power estimation, this capability leads in two directions, he said - early software development, and software-driven verification.
For software-driven verification, Mehta said, "we built a core platform that shows the CPU subsystem, I/O subsystem, interrupt subsystem, and memory subsystem. We boot Linux on it. Then we show a migration path that goes from TLM all the way to RTL for design and verification."
While the Cadence Virtual System Platform provides the virtual prototyping aspects of this flow, the Incisive Verification Platform brings in RTL simulation and testbench automation, and the Palladium XP Verification Computing Platform provides RTL acceleration. The result is a hybrid TLM/RTL simulation capability. Jose Fernandez, solutions group director at Cadence, noted this provides a couple of important capabilities. One is the ability to use legacy IP while still maintaining the fast performance of a virtual prototype. Another is a migration path from TLM to RTL during verification, making it possible to substitute RTL for testing such components as device drivers.
The reference flow also includes what TSMC calls iPPA, which stands for power, performance and area modeling for specific process nodes. These models are available to the SystemC TLM models through an API, making it possible to bring process-specific power, performance and area data into virtual prototyping for architectural analysis or software execution.
So how is ESL verification different in Reference Flow 12, compared to the block-level approach in Reference Flow 11? "This time around," Mehta said, "you verify a block at the TLM level, then you measure coverage, and then you plug that block into a virtual platform. Then you reuse that coverage when you verify the virtual platform. Then, you take the same TLM model and use it as a reference model for RTL, where you have a lot more facility in terms of coverage."
It's All About Power
Why would a foundry care about early software development and architectural analysis? According to Mehta, the answer is power. In order to adequately estimate and manage power, he noted, it's necessary to build virtual platforms and do software development. "We want to enable the entire ecosystem so people can meaningfully do power analysis," he said. "Power is the center pole, and everything else surrounds it."
TSMC Reference Flow 12 provides strong validation for the Virtual System Platform and for the interconnected nature of the System Development Suite. It's also another strong endorsement by TSMC of ESL methodologies in general, and as such, is another step forward for System Realization as described in the EDA360 vision.
This is indeed interesting and encouraging that a foundary is taking such an interest in System Level power solutions. Makes sense since Power and Software/Verification developments are making or breaking multi-core projects.
India is beginning to get into ESL what with it's vast talent pool in software. With emerging TLM2.0 standard, India can provide a big boost to this field with services and products.