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While all process node migrations have posed challenges, the move to 20nm may be more challenging than most. At this process node, lithography is so difficult that extra masks (double patterning) will be widely deployed. But despite the costs and challenges, the promise of higher performance and lower power is attractive to many chip design companies, and interest is keen, according to Ana Hunter, vice president of foundry services at Samsung.
In this interview Hunter discusses design and process challenges of 20nm, the benefits of Samsung's high-k metal gate (HKMG) technology, double patterning, design rules, and other attributes of this new process node. She also describes a 20nm test chip project recently completed with ecosystem partners including Cadence. For more information about this project, which used the Cadence unified RTL-to-GDSII digital flow, see the July 11 Cadence press release.
Q: Ana, Is the move to 20nm just another process node migration, or does it pose some unusual challenges?
A: It's a little more than the process node changes we've had in the past. We've always introduced new things from one technology to another, but I think people are looking at double patterning as a unique challenge for designers. On the process side we have other challenges as well.
Q: What changes are you seeing on the process side?
A: At 20nm we will have HKMG, which we already started using at 32/28nm. We are transitioning from gate-first at 32/28 to gate-last at 20nm. We will also have a lot more strain engineering at 20nm, so we'll have elevated source drains, and additional stress applied to improve mobility while keeping the leakage under control.
Q: Why gate-first at 32/28nm, and gate-last at 20nm?
A: At 32/28nm, gate-first gave us a lot of flexibility. It allowed a pretty simple migration from 45nm because nothing was really different on the design side. We didn't have the restricted design rules we'll have at 20nm.
Because of the lithography, 20nm introduces a lot of restrictions on design rules, so we thought this was a good point to go from gate-first to gate-last. The gate-last approach has more restrictions, but at 20nm we have restricted rules anyway, so there aren't additional restrictions for gate-last. We can increase the performance by going to gate-last.
Q: How much of a performance gain are you seeing at 20nm?
A: From 28nm to 20nm we're seeing about a 35% performance improvement at the same leakage level. We're seeing about a 50% leakage reduction at the same performance. This is not just because of gate-last; it's also because of added stress, and other things.
Q: Will 20nm require double patterning for all designs? And for which layers?
A: If you need the density to get below 80nm metal pitches, you will need to go to double patterning. If you don't need to go below 80nm, you don't need double patterning. We expect most customers to use [double patterning] because otherwise, the shrink from 28nm to 20nm doesn't provide enough density.
The double patterning is needed on metal one and some of what we call "metal X" layers. It depends on the customer's design techniques, and how many 64nm layers they want to use. For example, power routing uses wider pitches that may not need 64nm.
Q: What design challenges does double patterning pose?
A: Because you're splitting a layer into two masks, you're doing two different patterns and two different etches. There are alignment issues and CD [critical dimension] variations that need to be taken into account. There could be some misalignment.
Q: How much will double patterning increase NRE costs?
A: It's a little early to say how much. There are so many variables, including how many double patterning layers you're going to use. Obviously it is a more expensive technology. For early adopters the masks at 20nm will be more expensive, but early adopters are willing to pay more NRE to get to market earlier.
Q: How "restricted" are the restricted design rules at 20nm?
A: Our design kits give customers some options. For instance, if they do all their transistors in one direction they can expect this much variation; if they want to orient transistors in the X and Y directions they can expect that much variation. At 20nm it is generally expected that all transistors will be in a single direction, but some customers ask for two directions in I/Os. We typically allow for that, but there will be more variation, because the lithography is optimized for one direction.
Q: Where is the interest in 20nm coming from?
A: We've seen a lot of interest in mobile processors. Customers are really into the GHz race even for mobile phones and tablets. These kinds of applications are going very quickly to 28nm and they're asking for 20nm. We're also seeing interest from high-performance networking applications and graphics applications, where designers are always looking for as many GHz as they can get.
Q: When do you expect to be in production with 20nm?
A: Our schedule calls for us to have qualified 20nm toward the end of the year. We expect customers to ramp into significant volumes in the second half of 2013.
Q: You recently completed a 20nm HKMG test chip, based on an ARM Cortex-M0 processor, with Cadence and other partners. What was involved with that effort?
A: The test chip is a collaborative effort to develop the ecosystem for 20nm and to work on things we've been talking about, like double patterning. We worked with Cadence mostly on the routing side.
We're collaborating to develop an entire ecosystem along with process developments, design rules, design kits, technology files, and so on. A partner might say, "if we can change this rule, it will make a difference in the libraries and the routing." It's important to do this work early on because as you get closer to the time the process is qualified, changes become very expensive.
Q: In conclusion, what do you want customers to know about 20nm?
A: It's looking very good. 20nm results out of our R&D labs are very close to achieving the desired performance. We're very optimistic about 20nm.
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