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It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced digital verification methodologies can be used to verify mixed-signal SoCs.
The webinar is titled "Applying Digital Verification Methodologies to Analog Design." The webinar shows how to approach analog block integration regardless of abstraction level, and how to increase verification quality using metric-driven verification (MDV), an approach that has become commonplace in the digital world.
Why is this important? Kishore Karnane, Cadence product marketing director, started the webinar by noting an industry study that showed that 70% of chip respins at 65nm and 45nm are due to problems with mixed-signal functionality. Moreover, 95% of designs at 65nm and 45nm have some mixed-signal functionality. "Verifying transfer functions and corner cases is not sufficient any more. We need to augment analog verification by applying digital verification methodologies to analog design," Karnane said.
Bridging Two Worlds
Karnane presented two mixed-signal verification use models. The analog-centric model is schematic-based, and uses transistor-level simulation and corner analysis. The digital-centric model is command-line driven, and uses MDV with random testbenches, coverage, and verification planning. What ties these use models together is real number models. This capability, available in languages such as Verilog and Verilog-AMS, allows real data types that represent analog values in digital simulations.
Dan Romaine, staff solutions engineer at Cadence, made the case for MDV for analog/mixed-signal design. MDV, he said, "is a way of starting with verification planning up front and using a variety of metrics to drive verification all the way through to tapeout." He noted that "we are not saying you should throw away Spice level verification. What we want to do is find additional ways to make sure you're not missing any bugs when integrating an [analog] IP block into an SoC."
Citing the Universal Verification Methodology (UVM) standard developed by Accellera, Romaine said that "we want to apply these [UVM] techniques and build analog-centric reusable verification components that can generate the unique analog stimulus you need, and write reusable tests at the analog level in a functional way for the IP that's connected into your digital logic. And then, we want to collect coverage and do automatic checking at the analog level."
Romaine talked about the basic steps in the MDV process, including constructing an executable test plan, building testbenches, executing tests, and measuring and analyzing metrics. These steps are shown below.
Metric-driven verification overview
For the rest of the one-hour webinar, Romaine delved into the details of the following steps:
Creating an Executable Verification Plan. Romaine showed how the Cadence Incisive Enterprise Planner tool can be used to create an executable plan that includes electrical objects, and links coverage elements to these objects.
Model Creation and Validation. Romaine showed how real number modeling can model analog block operation as discrete real data, allowing very fast simulator performance. He discussed the Verilog-AMS wreal data type along with a Cadence implementation that permits multiple drivers on a net, X and Z states, and wreal arrays. He noted that continual model validation is mandatory for analog behavioral models, and showed how a Cadence tool called amsDMV can help automate this task.
Testbench Creation. Romaine showed a UVM-MS (mixed-signal UVM) environment that can be used to simulate an analog IP block in a mixed-signal SoC. The environment is based on reusable code, and it generates the UVM test sequences that drive the analog signals, checks, and coverage. At present this solution is based on the e language.
Analyze Results and Measure Coverage. After simulation is run, Romaine noted, the Cadence Incisive Enterprise Manager can collect all the data from all the runs and provide analog and digital coverage information in a single view. Users can see how much coverage was achieved for various parts of the plan.
Stepping beyond the webinar for a moment, I know from a recent experience that IC design companies are bringing digital verification methodologies into mixed-signal environments. I moderated a Design Automation Conference panel in which engineers from Qualcomm, NXP, and LSI discussed how they are doing just that (reported in this blog post). The free webinar described above is time well spent for anyone facing the challenge of analog IP integration into mixed-signal SoCs - and today, virtually all SoCs pose this challenge.